ULTRA HQX
Abstract: MS62256L-10 MS62256 MS62256L-12 MS62256L-70 MS62256L-70FC MS62256L-85 T-46 ms62256l-70pc MS62256L10PC
Text: S4E » b3533Tl 00D13TÏ 311 MOSEL IMOVI MS62256 32K x 8 CMOS Static RAM MOSEL-VITELIC r r -4 1 0 -2 3 -1 3 » FEATURES DESCRIPTION • High-speed - 70/85/100/120 ns The MOSEL M S62256 is a 262,144-bit static random access memory organized as 32,768 words by 8 bits and
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b3533Tl
DDD13TÃ
MS62256
MS62256L
385mW
MS62256
144-bit
MS622iod,
500mV
MS62256L-70FC
ULTRA HQX
MS62256L-10
MS62256L-12
MS62256L-70
MS62256L-85
T-46
ms62256l-70pc
MS62256L10PC
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kexz
Abstract: No abstract text available
Text: MOSEL-VITELIC b2E » MOSEL-VITELIC • b3533Tl GGGS33L. GES ■ M O V I V104J232, V104J236 512K X 32, 512K x 36 SIMM PRELIMINARY Features Description a 524,288 x 32 bit or 524,288 x 36 bit The V104J232 Memory Module is organized as 524,288 x 32 bits in a 72-lead single-in-line module.
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b3533Tl
GGGS33L.
V104J232,
V104J236
72-lead
V104J232
QDQE34A
104J232/236
kexz
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weitek
Abstract: 80386 chipset block diagram of 80386 microprocessor 82c331
Text: flOSEL-VITELIC 4ÔE D MOSEL • b3533Tl OODlOb? 3 ■ UOVI Product Brief MS82C330 Cache Chipset for 80386 Systems with Write-Thru Cache FEATURES Quad fetch mode uses 16 byte subblocks for improved hit rate - Demand word fetch first strategy reduces miss penalty
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b3533Tl
MS82C330
MS82C331
MS82C332
MS82C333
64Kbyte
PID035
weitek
80386 chipset
block diagram of 80386 microprocessor
82c331
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Untitled
Abstract: No abstract text available
Text: S4E J> b3533Tl D0D1377 7SQ • MOVI MOSEL MS6264 8K x 8 CMOS StaticRAM n O S E L - V l T E L I C FEATURES DESCRIPTION • Available in 70/100 ns Max. The MOSEL MS6264 is a high performance, low power CMOS static RAM organized as 8192 words by 8 bits. The
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b3533Tl
D0D1377
MS6264
MS6264
495mW
S6264-70PC
P28-1
S6264-70FC
S28-2
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PDF
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Untitled
Abstract: No abstract text available
Text: SME » b3533Tl DDDmOb 3fll MOSEL novi MS62256C 32K x 8 CMOS Static RAM nO-SEL-VITELIC FEATURES DESCRIPTION • High-speed - 70/100/120/150 ns The MOSEL MS62256C is a 262,144-bit static random access memory organized as 32,768 words by 8 bits and operates from a single 5 volt supply. It is built with
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b3533Tl
MS62256C
MS62256C
144-bit
28pin
440mW
MS62256C)
MS62256C-70PC
P28-4
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7202A
Abstract: No abstract text available
Text: M OSEL V ITEU C MS7200U7201AL/7202AL 256x9,512x9, 1Kx9 CMOS FIFO Features Descriptions • First-In/First-Out static RAM based dual port memory ■ Three densities in a x9 configuration ■ Low power versions ■ Includes empty, full, and half full status flags
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MS7200U7201AL/7202AL
256x9
512x9,
MS7200L/7201AL/7202AL
MS7200-25NC
MS7200-25JC
MS7200-25FC
MS7200-35NQ
MS7200-35JC
MS7200-35FC
7202A
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Untitled
Abstract: No abstract text available
Text: M O SEL VITELIC V53C311616500 3.3 VOLT 1 M X 16 EDO PAGE MODE CMOS DYNAMIC RAM HIGH PERFORMANCE 50 60 70 Max. RAS Access Time, Irac 50 ns 60 ns 70 ns Max. Column Address Access Time, (^ aa) 25 ns 30 ns 35 ns Min. Extended Data Out Page Mode Cycle Time, fcc)
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V53C311616500
16-bit
cycles/64
42-pin
50/44-pin
V53C311616500
G0G4151
00QM1S2
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Untitled
Abstract: No abstract text available
Text: MOSEL VITELIC V53C316580500 3.3 VOL T 8 M X 8 EDO PA GE MODE CMOS DYNAMIC RAM 40 50 60 Max. RAS Access Time, tRAC 40 ns 50 ns 60 ns Max. Column Address Access Time, (tcM) 20 ns 25 ns 30 ns Min. EDO Page Mode Cycle Time, (tPC) 16 ns 20 ns 25 ns Min. Read/Write Cycle Time, (tRC)
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V53C316580500
V53C316580500
cycles/64
32-pin
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V53C8256H
Abstract: No abstract text available
Text: MOSEL VITELIC V53C8256H ULTRA-HIGH PERFORMANCE, LOW POWER 256KX 8 BIT FAST PAGE MODE CMOS DYNAMIC RAM HIGH PERFORMANCE PRELIMINARY 35 40 45 50 Max. RAS Access Time, tRAc 35 ns 40 ns 45 ns 50 ns Max. Column Address Access Time, (tCAA) 18 ns 20 ns 22 ns 24 ns
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V53C8256H
256KX
V53C8256H
24-pin
26/24-pin
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Untitled
Abstract: No abstract text available
Text: MOSEL-VITELIC 4ûE D • ta3S33Tl 0 0 0 0 7 0 7 MOSEL T ■ HO MS6264A 8K x 8 High Speed CMOS Static RAM T -4 6 -2 3 -1 2 FEATURES DESCRIPTION • High spaed - 45/55 ns Max. The MOSEL MS6264A is a high performance, low power CMOS static RAM organized as 8192 words by 8 bits. The
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ta3S33Tl
MS6264A
MS6264A
S6264AL-45N
P28-2
S6264AL-45P
P28-1
S6264AL-45S
S28-1
S6264AL-55N
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Untitled
Abstract: No abstract text available
Text: M O S E L V IT E L IC V53C818H H IG H PERFORM ANCE 5 1 2 K X 16 EDO PA GE MODE CMOS DYNAM IC RAM HIGH PERFO RM ANC E PRELIM INARY 30 35 40 45 50 Max. RAS Access Time, tRAc 30 ns 35 ns 40 ns 45 ns 50 ns Max. Column Address Access Time, (^ aa) 16 ns 18 ns
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V53C818H
16-bit
40-Pin
40/44L-Pin
V53CB18H
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Untitled
Abstract: No abstract text available
Text: M O S E L VÊTEL IC V53C8256H U LTR A -H IG H PERFO RM ANCE, L O W PO W ER 2 5 6 K X 8 B IT F A S T P A G E M O D E CM O S D YN A M IC R A M H IG H P E R F O R M A N C E Max. RAS Access Time, tRAC 4 5 /4 5 L 5 0 /5 0 L 5 5 /5 5 L 6 0 /6 0 L 45 ns 50 ns 55 ns
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V53C8256H
115ns
8256H
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Untitled
Abstract: No abstract text available
Text: bEE » MOSEL-VITELIC MOSEL- VITELIC • baSBB^l DDGSOSb 170 ■ MOVI V53C404F HIGH PERFORMANCE, LOW POWER 1 M X 4 BIT FAST PAGE MODE CMOS D YNAMIC RAM H IG H P E R F O R M A N C E V 5 3 C 4 0 4 F Max. RAS Access Time, tRAf. PRELIMINARY 6 0 /6 0 L 7 0 /7 0 L
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V53C404F
404FL
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Untitled
Abstract: No abstract text available
Text: nOSEL-VITELIC bSE ]> • b3S33Tl G0 Dlfl2ö b?b M M O V I V53C256A FAMILY HIGH PERFORMANCE, LOW POWER 2 5 6 K X 1 BIT FAST PAGE MODE CMOS DYNAMIC RAM MOSEL- VITELIC H IG H P E R F O R M A N C E V 5 3 C 2 5 6 A 6 0 /6 0 L 7Q /70L 8 0 /8 0 L 1 0 /1 0 L 60 ns
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b3S33Tl
V53C256A
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Untitled
Abstract: No abstract text available
Text: MOSEL VITELIC V43648Y04V C TG-75 3.3 VOLT 8M x 64 HIGH PERFORMANCE PC133 UNBUFFERED SODIMM Features PRELIMINARY The V 4 3648Y 04V (C )T G -75 memory module is organized 8 ,388,608 x 64 bits in a 144 pin S O D IM M . The 8M x 64 memory module uses 8 Mosel-Vitelic 4M x 16 SD R A M . The x64 modules
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V43648Y04V
TG-75
PC133
3648Y
TG-75-04
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Untitled
Abstract: No abstract text available
Text: MOSEL VITELIC INC. preliminary M SS2105/S3205/S4305/S6605 August 1996 2 1 '7 3 2 '7 4 3 '7 6 0 " V O IC E R O M Features Single power can operate at 2.4V through 6.0V. Current output could drive 8 ohm speaker with a transistor, Vout could drive buzzer directly.
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SS2105/S3205/S4305/S6605
55500h)
S6605
80000h)
PID24S*
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Untitled
Abstract: No abstract text available
Text: M O S E L V IT E L IC V53C8257H U LTR A -HIG H SPEED, 256KX 8B IT P A G E M O D E WITH E X TE N D E D DATA O U T P U T ED O A N D C A S B U R S T M O D E CM O S D YN A M IC R A M PR E LIM IN A R Y 45/45L 50/50L 55/55L 60/60L Max. RAS Access Time, Orac)
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V53C8257H
256KX
45/45L
50/50L
55/55L
60/60L
V53C8257H
VS3C8257H
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PDF
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Untitled
Abstract: No abstract text available
Text: M O SE L VITELIC PRELIMINARY V62C518256 32Kx8 BIT STATIC RAM Features Description • High-speed: 35,45, 55, 70 ns ■ Ultra low DC operating current of 5mA Max. ■ Low Power dissipation: TTL Standby: 3mA (Max.) CMOS Standby: 20n.A (Max.) ■ Fully static operation
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V62C518256
32Kx8
28-pin
V62C518256
144-bit
b3533Tl
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PDF
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Untitled
Abstract: No abstract text available
Text: M O SEL VTTEUC PRELIMINARY V104J232 512K x 32 SIMM Features Description 524,288 x 32 bit organizations Utilizes 256K x 4 CMOS DRAMs Fast access times 70 ns, 80 ns, 100 ns Fast Page mode operation Low power dissipation _ CAS before RAS refresh, RAS only refresh, and
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V104J232
72-lead
V104J232
DD03350
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Untitled
Abstract: No abstract text available
Text: M O S EL V IT E L IC V53C8129H ULTRA-HIGH PERFORMANCE, 128K X 8 BIT EDO PAGE MODE CMOS DYNAMIC RAM PRELIMINARY 35 40 45 50 Max. RAS Access Time, tRAC 35 ns 40 ns 45 ns 50 ns Max. Column Address Access Time, (Icu ò 18 ns 20 ns 22 ns 24 ns Min. Fast Page Mode With EDO Cycle Time, (tpC)
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V53C8129H
V53C8129H-50
24-pin
26/24-pin
QD03fl3b
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PDF
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Untitled
Abstract: No abstract text available
Text: M O S EL V IT E L IC V53C511816502 1M x 16 EDO PA G E M ODE CMOS DYNAM IC RAM OPTIONAL SE LF REFRESH HIGH PERFORMANCE 50 60 Max. RAS Access Time, Jrac 50 ns 60 ns Max. Column Address Access Time, (^;aa ) 25 ns 30 ns Min. Extended Data Out Page Mode Cycle Time, (1pC)
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V53C511816502
16-bit
cycles/16
42-pin
44/50-pin
V53C511816502
b3S33Tl
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PDF
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Untitled
Abstract: No abstract text available
Text: M O SEL VITELIC PREW BBtO M V62C51864 8Kx8 B IT STA TIC RAM Features Description • ■ ■ The V 62C 51864 is a 65,536-bit static random access memory organized as 8,192 words by 8 bits. It is built with M O SE L VITE LIC ’s high performance C M O S process. Inputs and three state outputs are
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V62C51864
536-bit
b3533
28-Pin
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PDF
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Untitled
Abstract: No abstract text available
Text: M O SEL V tTE LiC V53C8512N 3.3 VOLT, LO W POWER 512K x 8 AN D 5 1 2 K x 9 B IT FA S T PAGE MODE CMOS DYNAMIC RAM PRELIM INARY HIGH PERFORMANCE V53C8512N 60/60L 70/70L M ax. R A S A cce ss T im e, Orac 6 0 ns 70 ns M ax. C o lum n A d dre ss A cce ss T im e , tCAA)
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V53C8512N
60/60L
70/70L
V53C8S12NL
V53C8512N
January199S
b3S33
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v110h
Abstract: V53C104F
Text: M O S E L VTTELÊ C V53C 104F H IG H PE R FO RM A N CE, L O W P O W E R 2 5 6 K X 4 B IT F A S T P A G E M O D E CM O S D Y N A M IC R A M 60/60L 70/70L 80/80L Max. RAS Access Time, tRAC 60 ns 70 ns 80 ns Max. Column Address Access Time, (tCAA) 30 ns 35 ns
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V53C104F
V53C104F
60/60L
70/70L
80/80L
V53C104FL
200mA
200nA
V53C104F-80
V53C104F-1
v110h
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