Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    AXI MASTER Search Results

    AXI MASTER Result Highlights (6)

    Part ECAD Model Manufacturer Description Download Buy
    SCR410T-K03-10 Murata Manufacturing Co Ltd 1-Axis Gyro Sensor Visit Murata Manufacturing Co Ltd
    SCR410T-K03-05 Murata Manufacturing Co Ltd 1-Axis Gyro Sensor Visit Murata Manufacturing Co Ltd
    SCR410T-K03-004 Murata Manufacturing Co Ltd 1-Axis Gyro Sensor Visit Murata Manufacturing Co Ltd
    SCC433T-K03-004 Murata Manufacturing Co Ltd 2-Axis Gyro, 3-axis Accelerometer combination sensor Visit Murata Manufacturing Co Ltd
    SCC433T-K03-10 Murata Manufacturing Co Ltd 2-Axis Gyro, 3-axis Accelerometer combination sensor Visit Murata Manufacturing Co Ltd
    SCC433T-K03-05 Murata Manufacturing Co Ltd 2-Axis Gyro, 3-axis Accelerometer combination sensor Visit Murata Manufacturing Co Ltd

    AXI MASTER Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    DS768

    Abstract: AMBA AXI4 verilog code axi4-lite and apb protocol AMBA AXI4 AMBA AXI to APB BUS Bridge vhdl code
    Text: LogiCORE IP AXI Interconnect v1.04.a DS768 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI


    Original     		PDF DS768 AMBA AXI4 verilog code axi4-lite and apb protocol AMBA AXI4 AMBA AXI to APB BUS Bridge vhdl code

    Untitled

    Abstract: No abstract text available
    Text: LogiCORE IP AXI Interconnect v1.06.a DS768 December 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI


    Original     		PDF DS768

    DS768

    Abstract: axi4-lite and apb protocol AMBA AXI to APB BUS Bridge vhdl code AXI4 lite verilog AMBA file write AXI verilog code AMBA AXI dma controller designer user guide
    Text: LogiCORE IP AXI Interconnect v1.06.a DS768 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI


    Original     		PDF DS768 ZynqTM-7000, axi4-lite and apb protocol AMBA AXI to APB BUS Bridge vhdl code AXI4 lite verilog AMBA file write AXI verilog code AMBA AXI dma controller designer user guide

    axi ethernet lite software example

    Abstract: microblaze axi ethernet lite zynq axi ethernet software example microblaze ethernet lite fpga cdma by vhdl examples DS787
    Text: LogiCORE IP AXI Ethernet Lite MAC v1.01.b DS787 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The Advanced Microcontroller Bus Architecture (AMBA ) Advanced eXtensible Interface (AXI) AXI Ethernet Lite MAC (Media Access Controller) is


    Original     		PDF DS787 axi ethernet lite software example microblaze axi ethernet lite zynq axi ethernet software example microblaze ethernet lite fpga cdma by vhdl examples

    AXI4 lite verilog

    Abstract: AMBA AXI verilog code AMBA AXI4 verilog code AXI4 verilog AMBA AXI specifications AMBA AXI4 cdn_axi4_slave_bfm DS824 axi bfm axi wrapper
    Text: AXI Bus Functional Models v2.1 DS824 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI Bus Functional Models BFMs , developed for Xilinx by Cadence Design Systems, support the simulation of customer-designed AXI-based IP. AXI


    Original     		PDF DS824 AXI4 lite verilog AMBA AXI verilog code AMBA AXI4 verilog code AXI4 verilog AMBA AXI specifications AMBA AXI4 cdn_axi4_slave_bfm axi bfm axi wrapper

    uart 16550

    Abstract: XC6SLX16CSG324 AMBA AXI4 XC6SLX16-CSG324 XC6VLX75T-FF784 uart vhdl fpga UART16550 V6 6D XC7V855T National Semiconductor PC16550D UART
    Text: LogiCORE IP AXI UART 16550 v1.01a DS748 June 22, 2011 Product Specification Introduction LogiCORE IP Facts Table The AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the AMBA (Advance Microcontroller Bus Architecture) AXI (Advanced


    Original     		PDF DS748 PC16550D uart 16550 XC6SLX16CSG324 AMBA AXI4 XC6SLX16-CSG324 XC6VLX75T-FF784 uart vhdl fpga UART16550 V6 6D XC7V855T National Semiconductor PC16550D UART

    state machine axi 3 protocol

    Abstract: XPS IIC xilinx vhdl rs232 code axi interconnect xilinx 0X138 ZYNQ-7000
    Text: LogiCORE IP AXI IIC Bus Interface v1.02a DS756 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI IIC Bus Interface connects to the Advanced Microcontroller Bus Architecture (AMBA ) specification’s Advanced eXtensible Interface (AXI)


    Original     		PDF DS756 state machine axi 3 protocol XPS IIC xilinx vhdl rs232 code axi interconnect xilinx 0X138 ZYNQ-7000

    XC6SLX45t-fgg484

    Abstract: XC6VLX240T-FF1156 awid communication protocol axi wrapper xc6slx45tfgg484 AXI4 verilog TM7000 Datasheet
    Text: LogiCORE IP ChipScope AXI Monitor v3.03.a DS810 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The ChipScope AXI Monitor core is designed to monitor and debug AXI interfaces. The core allows the probing of any signals going from a peripheral to the


    Original     		PDF DS810 TM-7000, XC6SLX45t-fgg484 XC6VLX240T-FF1156 awid communication protocol axi wrapper xc6slx45tfgg484 AXI4 verilog TM7000 Datasheet

    Untitled

    Abstract: No abstract text available
    Text: LogiCORE IP AXI INTC v1.04a DS747 June 19, 2013 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interrupt Controller (AXI INTC) core receives multiple interrupt inputs from peripheral devices and merges them to a single


    Original     		PDF DS747

    XC6SLX16-CSG324

    Abstract: XC6SLX16CSG324 uart 16550 HOLDING UART16550 16550 uart timing XC7K410TFFG676-3
    Text: LogiCORE IP AXI UART 16550 v1.01a DS748 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the AMBA (Advance Microcontroller Bus Architecture) AXI (Advanced


    Original     		PDF DS748 PC16550D PC165otify XC6SLX16-CSG324 XC6SLX16CSG324 uart 16550 HOLDING UART16550 16550 uart timing XC7K410TFFG676-3

    Untitled

    Abstract: No abstract text available
    Text: LogiCORE IP AXI INTC v1.03a DS747 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interrupt Controller (AXI INTC) core receives multiple interrupt inputs from peripheral devices and merges them to a single


    Original     		PDF DS747

    BP131

    Abstract: CL013G arm axi
    Text: PrimeCell Infrastructure AMBA 3 AXI Downsizer BP131 Revision: r0p0 Technical Overview This Technical Overview describes the functionality of the AXI downsizer in the following sections: • Preliminary material on page 2 • About the AXI downsizer on page 4


    Original     		PDF BP131) BP131 CL013G arm axi

    Untitled

    Abstract: No abstract text available
    Text: LogiCORE IP AXI Quad Serial Peripheral Interface AXI Quad SPI v2.00a DS843 December 18, 2012 Product Specification Introduction LogiCORE IP Facts The AXI Quad SPI connects the AXI4 interface to those SPI slave devices that support Standard, Dual or Quad


    Original     		PDF DS843 M68HC11 Zynq-7000

    axi interconnect xilinx

    Abstract: axi3
    Text: LogiCORE IP AXI External Slave Connector v1.00.a DS805 January 18, 2012 Product Specification Introduction LogiCORE IP Facts Table AXI External Slave Connector (axi_ext_slave_conn), lets you connect an AXI slave device outside of the embedded system module, using embedded module


    Original     		PDF DS805 ZynqTM-7000, axi interconnect xilinx axi3

    xc6vlx130t-ff1156

    Abstract: XILINX ipic axi
    Text: LogiCORE IP AXI Serial Peripheral Interface AXI SPI (v1.02.a) DS742 January 18, 2012 Product Specification Introduction LogiCORE IP Facts The AXI Serial Peripheral Interface (SPI) connects to the Advanced eXtensible Interface (AXI4). This core provides a serial interface to SPI devices such as SPI


    Original     		PDF DS742 M68HC11 32-bit xc6vlx130t-ff1156 XILINX ipic axi

    Xilinx Spartan-6 LX4

    Abstract: DS817 spartan6 jtag instruction spartan 6 LX150 fifo generator xilinx spartan state machine axi axi crossbar Xilinx Spartan 6 LX75 icape2 state machine axi 3 protocol
    Text: LogiCORE IP AXI HWICAP v2.02.a DS817 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP Advanced eXtensible Interface (AXI) HWICAP (Hardware Internal Configuration Access Port) core for the AXI Interface


    Original     		PDF DS817 ZynqTM-7000, Xilinx Spartan-6 LX4 spartan6 jtag instruction spartan 6 LX150 fifo generator xilinx spartan state machine axi axi crossbar Xilinx Spartan 6 LX75 icape2 state machine axi 3 protocol

    N25Q256

    Abstract: WINBOND W25Q80 XC7K325TFFG900 XC6VLX130TFF1156 W25Q64VSFIG XC7K325T W25Q64vs axi4 DS843 W25Q80
    Text: LogiCORE IP AXI Quad Serial Peripheral Interface AXI Quad SPI (v1.00a) DS843 October 19, 2011 Product Specification Introduction LogiCORE IP Facts The AXI Quad Serial Peripheral Interface connects the AXI4 interface to SPI slave devices that support the


    Original     		PDF DS843 M68HC11 N25Q256 WINBOND W25Q80 XC7K325TFFG900 XC6VLX130TFF1156 W25Q64VSFIG XC7K325T W25Q64vs axi4 W25Q80

    XC7K325TFFG900

    Abstract: W25Q64VSFIG WINBOND W25Q80 SPARTAN 6 spi numonyx XPS ipic burst axi4 example Quad SPI N25Q256 NUMONYX xilinx spi XC7V285TFFG784-3 XC7K325T-ffg900
    Text: LogiCORE IP AXI Quad Serial Peripheral Interface AXI Quad SPI (v2.00a) DS843 July 25, 2012 Product Specification Introduction LogiCORE IP Facts The AXI Quad SPI connects the AXI4 interface to those SPI slave devices that support Standard, Dual or Quad


    Original     		PDF DS843 M68HC11 Zynq-7000 XC7K325TFFG900 W25Q64VSFIG WINBOND W25Q80 SPARTAN 6 spi numonyx XPS ipic burst axi4 example Quad SPI N25Q256 NUMONYX xilinx spi XC7V285TFFG784-3 XC7K325T-ffg900

    XC6SLX45t-fgg484

    Abstract: XC6VLX240T-FF1156 xc6vlx240tff1156-1 AMBA AXI4 stream specifications XC6VLX240T-FF1156-1 xc6vlx240tff1156 xc6slx45tfgg484 XC6SLX45T kintex 7 AMBA AXI designer user guide
    Text: LogiCORE IP ChipScope AXI Monitor v3.01.a DS810 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The ChipScope AXI Monitor core is designed to monitor and debug AXI interfaces. The core allows the probing of any signals going from a peripheral to the


    Original     		PDF DS810 XC6SLX45t-fgg484 XC6VLX240T-FF1156 xc6vlx240tff1156-1 AMBA AXI4 stream specifications XC6VLX240T-FF1156-1 xc6vlx240tff1156 xc6slx45tfgg484 XC6SLX45T kintex 7 AMBA AXI designer user guide

    AMBA AXI verilog code

    Abstract: BP130 verilog code for amba ahb master AMBA file write AXI verilog code CL013G AMBA AHB to AXI
    Text: PrimeCell Infrastructure AMBA 3 AXI Register Slice BP130 Revision: r0p0 Technical Overview ™ This technical overview describes the functionality of the AXI register slice in the following sections: • Preliminary material on page 2 • About the AXI register slice on page 4


    Original     		PDF BP130) AMBA AXI verilog code BP130 verilog code for amba ahb master AMBA file write AXI verilog code CL013G AMBA AHB to AXI

    AMBA AXI verilog code

    Abstract: BP132 CL013G block diagram for asynchronous FIFO AMBA AXI Logic diagram for asynchronous FIFO awid ARM verilog code AMBA file write AXI verilog code
    Text: PrimeCell Infrastructure AMBA 3 AXI Asynchronous Bridge BP132 Revision: r0p1 Technical Overview This technical overview describes the functionality of the AXI asynchronous bridge in the following sections: • Preliminary material on page 2 • About the AXI asynchronous bridge on page 3


    Original     		PDF BP132) 0023B AMBA AXI verilog code BP132 CL013G block diagram for asynchronous FIFO AMBA AXI Logic diagram for asynchronous FIFO awid ARM verilog code AMBA file write AXI verilog code

    28F00AP30

    Abstract: 28F00AP30TF IS61LVPS25636A XC6SL* MEMORY NUMONYX XILINX ipic axi DW10A emc core Spartan-6 FPGA
    Text: LogiCORE IP AXI External Memory Controller v1.03a DS762 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI External Memory Controller EMC IP core provides a control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular RAM


    Original     		PDF DS762 ZynqTM-7000 28F00AP30 28F00AP30TF IS61LVPS25636A XC6SL* MEMORY NUMONYX XILINX ipic axi DW10A emc core Spartan-6 FPGA

    XC6SLX16-2CSG324

    Abstract: IPIF XC6SLX16-2 AMBA AXI designer user guide axi interrupt xilinx XC6VLX130T-1-FF1156 XPS ipic axi DS768 XILINX ipic axi XC7K410TFFG676-3
    Text: LogiCORE IP AXI GPIO v1.01.b DS744 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP Advanced eXtensible Interface General Purpose Input/Output (AXI GPIO) core provides a general purpose input/output interface


    Original     		PDF DS744 32-bit ZynqTM-7000 XC6SLX16-2CSG324 IPIF XC6SLX16-2 AMBA AXI designer user guide axi interrupt xilinx XC6VLX130T-1-FF1156 XPS ipic axi DS768 XILINX ipic axi XC7K410TFFG676-3

    XC6VLX130T-1FF1156

    Abstract: XILINX FIFO UART uart 19200 ise one stop bit XC6VLX130T-1-FF1156 FF1156 fgg484 Xilinx ISE Design Suite 14.2 XC7K410TFFG676-3 XC6VLX130T block diagram UART using VHDL
    Text: LogiCORE IP AXI UART Lite v1.02a DS741 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Universal Asynchronous Receiver Transmitter (UART) Lite interface connects to the Advanced Microcontroller Bus Architecture


    Original     		PDF DS741 ZynqTM-7000 XC6VLX130T-1FF1156 XILINX FIFO UART uart 19200 ise one stop bit XC6VLX130T-1-FF1156 FF1156 fgg484 Xilinx ISE Design Suite 14.2 XC7K410TFFG676-3 XC6VLX130T block diagram UART using VHDL