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    AND8002 Search Results

    AND8002 Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    AND8002 On Semiconductor ECLinPS Lite and ECLinPS Plus Device Type and Date Code Guide Original PDF
    AND8002D On Semiconductor ECLinPS, ECLinPS Lite, ECLinPS Plus ECLinPS MAX, and GigaComm Marking and Ordering Information Guide Original PDF

    AND8002 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    On semiconductor date Code

    Abstract: motorola MARKING CODE SO-8 MOTOROLA LOT MARKINGS BRD8011/D marking code motorola ic Date Code Formats motorola traceability code 2012 Identification Traceability marking code onsemi Diode date sheet of ba for the year 2011
    Text: AND8002/D ECLinPS , ECLinPS Lite™, ECLinPS Plus™, ECLinPS MAX™, and GigaComm™ Marking and Ordering Information Guide http://onsemi.com APPLICATION NOTE Prepared by: Paul Shockman ON Semiconductor HFPD Applications Engineer Introduction This application note describes the device markings and


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    PDF AND8002/D On semiconductor date Code motorola MARKING CODE SO-8 MOTOROLA LOT MARKINGS BRD8011/D marking code motorola ic Date Code Formats motorola traceability code 2012 Identification Traceability marking code onsemi Diode date sheet of ba for the year 2011

    KLT20

    Abstract: k1648 klt22 KEL32 MC100 HEP64 KLT21 LP17 KEP32 HEP139
    Text: AND8002/D ECLinPS, ECLinPS Lite, ECLinPS Plus, ECLinPS MAX, and GigaComm Marking and Ordering Information Guide http://onsemi.com APPLICATION NOTE Prepared by: Paul Shockman ON Semiconductor HFPD Applications Engineer Introduction This application note describes the device markings and


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    PDF AND8002/D KLT20 k1648 klt22 KEL32 MC100 HEP64 KLT21 LP17 KEP32 HEP139

    kvt22

    Abstract: KVL11 KPT23 ON Semiconductor marking k1648 KLT20 HEL16 KEL32 KEL01 xaa9646
    Text: AND8002/D ECLinPS, ECLinPS Lite and ECLinPS Plus Device Type and Date Code Marking Guide Gary Richards, ECL Logic Product Engineering http://onsemi.com APPLICATION NOTE need ON Semiconductor’s marking spec 12MON00232D and S.O.P. 7–19 ID of Products to Location of


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    PDF AND8002/D 12MON00232D r14525 kvt22 KVL11 KPT23 ON Semiconductor marking k1648 KLT20 HEL16 KEL32 KEL01 xaa9646

    MOTOROLA LOT MARKINGS

    Abstract: On semiconductor date Code IC Lot Code Identification marking code 6L QFN tray qfn 4x4 AND8002 ase qfn unisem QFN marking code onsemi Diode on alpha year and work week
    Text: AND8002/D Clock Generation and Clock and Data Marking and Ordering Information Guide http://onsemi.com Prepared by: Paul Shockman ON Semiconductor APPLICATION NOTE Introduction This application note describes the device markings and ordering information for the following ON Semiconductor


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    PDF AND8002/D MOTOROLA LOT MARKINGS On semiconductor date Code IC Lot Code Identification marking code 6L QFN tray qfn 4x4 AND8002 ase qfn unisem QFN marking code onsemi Diode on alpha year and work week

    On semiconductor date Code

    Abstract: AND8002 AA MARKING CODE SO8 on alpha year and work week date code for semiconductor MOTOROLA LOT MARKINGS On semiconductor LQFP-52 motorola MARKING CODE SO-8 ON Semiconductor marking code
    Text: AND8002/D ECLinPS , ECLinPS Lite™, ECLinPS Plus™, ECLinPS MAX™, and GigaComm™ Marking and Ordering Information Guide http://onsemi.com APPLICATION NOTE Prepared by: Paul Shockman ON Semiconductor HFPD Applications Engineer Introduction This application note describes the device markings and


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    PDF AND8002/D On semiconductor date Code AND8002 AA MARKING CODE SO8 on alpha year and work week date code for semiconductor MOTOROLA LOT MARKINGS On semiconductor LQFP-52 motorola MARKING CODE SO-8 ON Semiconductor marking code

    HEL16

    Abstract: DEVICE MARKING CODE table onsemi marking marking code onsemi marking code onsemi Diode kel33 on semiconductor traceability marking soic HEL32 HEL12 HEL31 HEL05
    Text: AND8002/D ECLinPS, ECLinPS Lite, ECLinPS Plus, ECLinPS MAX, and GigaComm Marking and Ordering Information Guide http://onsemi.com APPLICATION NOTE Prepared by: Paul Shockman ON Semiconductor HFPD Applications Engineer Introduction This application note describes the device markings and


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    PDF AND8002/D HEL16 DEVICE MARKING CODE table onsemi marking marking code onsemi marking code onsemi Diode kel33 on semiconductor traceability marking soic HEL32 HEL12 HEL31 HEL05

    NB6N11SMNG

    Abstract: No abstract text available
    Text: NB6N11S 3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator Description The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical


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    PDF NB6N11S NB6N11S/D NB6N11SMNG

    Untitled

    Abstract: No abstract text available
    Text: NB3N106K 3.3V Differential 1:6 Fanout Clock Driver with HCSL Outputs Description The NB3N106K is a differential 1:6 Clock fanout buffer with High−speed Current Steering Logic HCSL outputs optimized for ultra low propagation delay variation. The NB3N106K is designed


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    PDF NB3N106K NB3N106K/D

    5621 transistor

    Abstract: 4gd1
    Text: NB6L295 2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential LVPECL Outputs Multi−Level Inputs w/ Internal Termination The NB6L295 is a Dual Channel Programmable Delay Chip http://onsemi.com designed primarily for Clock or Data de−skewing and timing


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    PDF NB6L295 QFN-24 NB6L295/D 5621 transistor 4gd1

    100EL91

    Abstract: MC100EL91 MC100EL91DW MC100EL91DWR2 MC100LVEL91
    Text: MC100EL91 3.3V / 5VĄTriple LVPECL / PECL Input to -5V ECL Output Translator The MC100EL91 is a triple LVPECL / PECL input to ECL output translator. The device receives standard or low voltage differential PECL signals, determined by the VCC supply level, and translates them


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    PDF MC100EL91 MC100EL91 MC100LVEL91. r14525 MC100EL91/D 100EL91 MC100EL91DW MC100EL91DWR2 MC100LVEL91

    E212 transistor

    Abstract: E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400
    Text: MC10E112, MC100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock


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    PDF MC10E112, MC100E112 MC10E/100E112 MC10E/100E111 r14525 MC10E112/D E212 transistor E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400

    AND8020

    Abstract: EL90 MC100EL90 MC100EL90DW MC100EL90DWR2 100EL90
    Text: MC100EL90 -3.3V / -5VĄTriple ECL Input to PECL Output Translator The MC100EL90 is a triple ECL to PECL translator. The device receives either –3.3 V or –5 V differential ECL signals, determined by the VEE supply level, and translates them to standard +5 V differential PECL


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    PDF MC100EL90 MC100EL90 r14525 MC100EL90/D AND8020 EL90 MC100EL90DW MC100EL90DWR2 100EL90

    KPT25

    Abstract: EPT25 MC100EPT25 MC100EPT25D MC100EPT25DR2 MC100EPT25DT MC100EPT25DTR2 KA25 kpt25 alyw
    Text: MC100EPT25 −3.3V / −5V Differential ECL to +3.3V LVTTL Translator The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, -3.3 V to -5.2 V, and ground. The small outline 8-lead package and the single gate of the EPT25 make it ideal


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    PDF MC100EPT25 MC100EPT25 EPT25 r14525 MC100EPT25/D KPT25 MC100EPT25D MC100EPT25DR2 MC100EPT25DT MC100EPT25DTR2 KA25 kpt25 alyw

    LQFP32

    Abstract: LQFP-32 MC100 MC100EPT622 MC100EPT622FA MC100EPT622FAR2
    Text: MC100EPT622 3.3V LVTTL/LVCMOS to LVPECL Translator The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The device has an OR- ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs


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    PDF MC100EPT622 MC100EPT622 MC100 EPT622 LQFP-32 r14525 MC100EPT622/D LQFP32 LQFP-32 MC100 MC100EPT622FA MC100EPT622FAR2

    KVT23

    Abstract: MC100LVELT23 MC100LVELT23D MC100LVELT23DR2 MC100LVELT23DT
    Text: MC100LVELT23 3.3V Dual Differential LVPECL to LVTTL Translator The MC100LVELT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which


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    PDF MC100LVELT23 MC100LVELT23 LVELT23 MC100LVELT23/D KVT23 MC100LVELT23D MC100LVELT23DR2 MC100LVELT23DT

    MC100EP90

    Abstract: MC100EP90DT MC100EP90DTR2 MC10EP90 MC10EP90DT MC10EP90DTR2
    Text: MC10EP90, MC100EP90 -3.3V / -5VĄTriple ECL Input to LVPECL/PECL Output Translator The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals.


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    PDF MC10EP90, MC100EP90 MC10/100EP90 r14525 MC10EP90/D MC100EP90 MC100EP90DT MC100EP90DTR2 MC10EP90 MC10EP90DT MC10EP90DTR2

    MC100E116

    Abstract: MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116
    Text: MC10E116, MC100E116 5VĄECL Quint Differential Line Receiver The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest.


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    PDF MC10E116, MC100E116 MC10E/100E116 r14525 MC10E116/D MC100E116 MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116

    MC100LVEL01

    Abstract: MC100LVEL01D 1085 SPICE model
    Text: MC100LVEL01 3.3VĄECL 4-Input OR/NOR The MC100LVEL01 is a 4–input OR/NOR gate. The device is functionally equivalent to the EL01 device and works from a 3.3 V supply. With AC performance similar to the EL01 device, the LVEL01 is ideal for low voltage applications which require the ultimate in


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    PDF MC100LVEL01 MC100LVEL01 LVEL01 KVL01 r14525 MC100LVEL01/D MC100LVEL01D 1085 SPICE model

    KEL04

    Abstract: HL04 HEL04 e104 MC100EL04 MC10EL04 HL-04
    Text: MC10EL04, MC100EL04 5VĄECL 2ĆInput AND/NAND The MC10EL/100EL04 is a 2-input AND/NAND gate. The device is functionally equivalent to the E104 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E104, the EL04 is ideally suited for those


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    PDF MC10EL04, MC100EL04 MC10EL/100EL04 AND8003/D r14525 MC10EL04/D KEL04 HL04 HEL04 e104 MC100EL04 MC10EL04 HL-04

    N100

    Abstract: NB100LVEP17 NB100LVEP17DT NB100LVEP17DTR2 NB100LVEP17MN TSSOP-20 qfn24 socket N100 transistor QFN-24
    Text: NB100LVEP17 2.5V / 3.3V / 5V ECL Quad Differential Driver/Receiver The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.


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    PDF NB100LVEP17 NB100LVEP17 r14525 NB100LVEP17/D N100 NB100LVEP17DT NB100LVEP17DTR2 NB100LVEP17MN TSSOP-20 qfn24 socket N100 transistor QFN-24

    KEP05

    Abstract: HEP05 MC100EP05 MC10EP05
    Text: MC10EP05, MC100EP05 3.3V / 5VĄECL 2-Input Differential AND/NAND The MC10/100EP05 is a 2–input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest AC performance


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    PDF MC10EP05, MC100EP05 MC10/100EP05 LVEL05 LVEL05 r14525 MC10EP05/D KEP05 HEP05 MC100EP05 MC10EP05

    EP809

    Abstract: MC100EP809 MC100EP809FA MC100EP809FAG MC100 SY89809L MC100EP809FAR2 MC100EP809FAR2G
    Text: MC100EP809 3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable http://onsemi.com Description The MC100EP809 is a low skew 1−to−9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into


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    PDF MC100EP809 MC100EP809 MC100EP809/D EP809 MC100EP809FA MC100EP809FAG MC100 SY89809L MC100EP809FAR2 MC100EP809FAR2G

    100EL91

    Abstract: MC100EL91 MC100LVEL91
    Text: MC100EL91 5 V Triple PECL Input to −5 V ECL Output Translator Description The MC100EL91 is a triple PECL input to ECL output translator. The device receives standard voltage differential PECL signals, determined by the VCC supply level, and translates them to differential


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    PDF MC100EL91 MC100EL91 MC100LVEL91. MC100EL91/D 100EL91 MC100LVEL91

    MC10EP016

    Abstract: MC100EP016 MC10E016
    Text: MC10EP016, MC100EP016 3.3V / 5V ECL 8−Bit Synchronous Binary Up Counter The MC10/100EP016 is a high−speed synchronous, presettable, cascadeable 8−bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS family. The counter features internal feedback to TC gated by the TCLD


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    PDF MC10EP016, MC100EP016 MC10/100EP016 MC10E016 MC10EP016/D MC10EP016 MC100EP016