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Catalog Datasheet	MFG & Type	Document Tags	PDF
64KX32 Abstract: 7C13 CY7C1329 Text: fax id: 1080 1CY 7C13 29 CY7C1329 PRELIMINARY 64K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1329 is 3.3V 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary	Original	CY7C1329 CY7C1329 100-MHz 64KX32 7C13	PDF
Untitled Abstract: No abstract text available Text: K7A163608A K7A163208A K7A161808A PRELIMINARY 512Kx36/x32 & 1Mx18 Synchronous SRAM Document Title 512Kx36/x32 & 1Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. 0.0 0.1 History Draft Date Remark 1. Initial draft 1. Add x32 org and industrial temperature	Original	K7A163608A K7A163208A K7A161808A 512Kx36/x32 1Mx18 1Mx18-Bit	PDF
K7A161801M Abstract: K7A163601M advh Text: K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM Document Title 512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 Initial draft Jan. 18. 1999 Preliminary 0.1 1. Update ICC & ISB values. 2. Remove tCYC 117MHz -85	Original	K7A163601M K7A161801M 512Kx36 1Mx18 1Mx18-Bit 117MHz 150mA 110mA 130mA K7A161801M K7A163601M advh	PDF
K d998 transistor Abstract: lz 02 1068 D844 voltage regulator Text: OMAP5912 Applications Processor Data Manual Literature Number: SPRS231E December 2003 − Revised December 2005 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include	Original	OMAP5912 SPRS231E SPRS231D SPRS231E. 289-ball K d998 transistor lz 02 1068 D844 voltage regulator	PDF
CY7C1382DV33-200BZI Abstract: No abstract text available Text: CY7C1380DV33 CY7C1382DV33 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades is 200 MHz ■ Registered inputs and outputs for pipelined operation	Original	CY7C1380DV33 CY7C1382DV33 18-Mbit CY7C1380DV33/CY7C1382DV33 CY7C1382DV33-200BZI	PDF
Untitled Abstract: No abstract text available Text: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)	Original	CY7C1347G CY7C1347G	PDF
CY7C1360C-250BGC Abstract: CY7C1360C CY7C1362C CY7C1360C-166BZI Text: CY7C1360C CY7C1362C PRELIMINARY 9-Mbit 256K x 36/512K x 18 Pipelined SRAM Functional Description[1] Features • • • • • • • • • • • • • • • • Supports bus operation up to 250 MHz Available speed grades are 250, 200, and 166 MHz	Original	CY7C1360C CY7C1362C 36/512K 250-MHz 200-MHz 166-MHz CY7C1360C-250BGC CY7C1360C CY7C1362C CY7C1360C-166BZI	PDF
CY7C1325G Abstract: CY7C1325G-133AXC CY7C1325G-133AXI CY7C1325G-133BGC CY7C1325G-133BGI CY7C1325G-133BGXC CY7C1325G-133BGXI Text: CY7C1325G PRELIMINARY 4-Mbit 256K x 18 Flow-Through Sync SRAM Functional Description[1] Features • 256K X 18 common I/O • 3.3V –5% and +10% core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version)	Original	CY7C1325G 133-MHz 117-MHz 100-MHz 100-pin 119-ball CY7C1325G CY7C1325G-133AXC CY7C1325G-133AXI CY7C1325G-133BGC CY7C1325G-133BGI CY7C1325G-133BGXC CY7C1325G-133BGXI	PDF
Transistor TT 2246 Abstract: TT 2206 datasheet apm 4906 TT 2206 transistor tt 2206 tt 2246 bt 7377 SOT-23 AAAA bc 5478 AAXZ Text: SOT TOPMARKS: 2 and 4 Letter ID Coding SOT Topmarks − April 24, 2005 Sorted By Part Number Sorted By Topmark Part Prefix Number Suffix Topmark Package Part Prefix Number Suffix Topmark Package LM 4040A EM3−2.1 FZNG 3/SOT−23 MAX 1916 ZT 1111 6/SOT−23	Original	3/SOT-23 6/SOT-23 10/uMAX 3/SC-70 Transistor TT 2246 TT 2206 datasheet apm 4906 TT 2206 transistor tt 2206 tt 2246 bt 7377 SOT-23 AAAA bc 5478 AAXZ	PDF
CY7C1327G Abstract: CY7C1327G-250AXC CY7C1327G-250AXI CY7C1327G-250BGC CY7C1327G-250BGI CY7C1327G-250BGXC CY7C1327G-250BGXI Text: CY7C1327G PRELIMINARY 4-Mbit 256K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 256K x18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times	Original	CY7C1327G 250-MHz 225-MHz 200-MHz CY7C1327G CY7C1327G-250AXC CY7C1327G-250AXI CY7C1327G-250BGC CY7C1327G-250BGI CY7C1327G-250BGXC CY7C1327G-250BGXI	PDF
a42 a331 Abstract: omap 310 TMS320C55x CSL USB VLYNQ C6000 OMAP5912 SPRU375 TMS320C6000 stt a227 a44 a331 Text: OMAP5912 ARM Chip Support Library Reference Guide Literature Number: SPRU816 August 2004 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any	Original	OMAP5912 SPRU816 accorda-24 Index-11 a42 a331 omap 310 TMS320C55x CSL USB VLYNQ C6000 OMAP5912 SPRU375 TMS320C6000 stt a227 a44 a331	PDF
Untitled Abstract: No abstract text available Text: OMAP5912 Applications Processor Data Manual Literature Number: SPRS231E December 2003 − Revised December 2005 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include	Original	OMAP5912 SPRS231E SPRS231D SPRS231E. 289-ball	PDF
WED2ZL361MSJ35BC Abstract: WED2ZL361MSJ38BC WED2ZL361MSJ42BC WED2ZL361MSJ Text: WED2ZL361MSJ White Electronic Designs 1M x 36 Synchronous Pipeline Burst NBL SRAM FEATURES DESCRIPTION n Fast clock speed: 250, 225, 200, 166, 150, 133MHz The WEDC SyncBurst - SRAM family employs high-speed, low-power CMOS designs that are fabricated using an	Original	WED2ZL361MSJ 133MHz WED2ZL361MSJ26BC WED2ZL361MSJ28BC WED2ZL361MSJ30BC WED2ZL361MSJ35BC WED2ZL361MSJ38BC WED2ZL361MSJ42BC WED2ZL361MSJ26BI* WED2ZL361MSJ28BI WED2ZL361MSJ35BC WED2ZL361MSJ38BC WED2ZL361MSJ42BC WED2ZL361MSJ	PDF
Untitled Abstract: No abstract text available Text: CY7C1361C CY7C1363C PRELIMINARY 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM Functional Description[1] Features • Supports 133-MHz bus operations The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed	Original	CY7C1361C CY7C1363C 36/512K 133-MHz CY7C1361C/CY7C1363C	PDF

adsh 13 Abstract: intel 80486 CY7C1031 CY7C1032 VXXXX Text: CY7C1031 CY7C1032 PRELIMINARY ?CYPRESS Functional Description continued Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) is LOW and (2) AD5P is LOW. ADSP-triggered write cycles are completed in two clock periods. The address at Ao	OCR Scan	CY7C1031 CY7C1032 CY7C1031 CY7C1032will 52-Lead CY7C1032- CY7C1032â CY7C1032-8NC adsh 13 intel 80486 CY7C1032 VXXXX	PDF
Untitled Abstract: No abstract text available Text: PRELIMINARY '# CYPRESS 32Kx 18 Synchronous Cache RAM Features • Direct interface with the processor and external cache controller • Supports 66-MHz Pentium micro processor cache systems with zero wait states • Asynchronous output enable • I/Os capable o f 3.3V operation	OCR Scan	66-MHz CY7C178) CY7C179) CY7C178 CY7C179 52-pin CY7C179â 52-Lead	PDF
10EZ11 Abstract: 1bw sot 23 W25P243AF-4 Text: Preliminary W25P243A sSSSs Electronics Corp. 64K x 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM GENERAL DESCRIPTION The W25P243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM organized as 65,536 x 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst	OCR Scan	W25P243A W25P243A -S77E555i: 5121fjii S52-27SS2Î S85-2 7-i37SC2 10EZ11 1bw sot 23 W25P243AF-4	PDF
Untitled Abstract: No abstract text available Text: W25P022A Gyinbond V fm v 64K x 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM Electronics Corp. GENERAL DESCRIPTION The W25P022A is a high-speed, low-power, synchronous-burst pipelined CMOS static RAM organized as 65,536 x 32 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst	OCR Scan	W25P022A W25P022A	PDF
Untitled Abstract: No abstract text available Text: CY7B173 CY7B174 CYPRESS SEMICONDUCTOR Features • S u p p orts 50-M H z cach e system s • 3 2 K by 9 com m on I/O • B iC M O S for op tim u m speed/pow er • 14-ns a ccess delay clock to ou tp u t • Two-bit w rap arou nd co u n ter su p p ort in g th e 486 b u rst seq u en ce (7B 173)	OCR Scan	CY7B173 CY7B174 14-ns --18LC --18L	PDF
00Q01 Abstract: ZQ50A BWRO Text: PRELIMINARY CY7C1337 32K x 32 Synchronous-Pipelined Cache RAM Features • Low 660 \|xW standby power (f=0, L version) • Supports 117-MHz bus operations with zero wait states • Fully registered Inputs and outputs for pipelined oper ation • 32K x 32 common I/O architecture	OCR Scan	CY7C1337 117-MHz 100-MHz 100TQFP 00Q01 ZQ50A BWRO	PDF
Untitled Abstract: No abstract text available Text: J5T ADVANCED INFORMATION CY82C694 Pentium hyperCache™ Chipset 128KB Expansion RAM Features • Interfaces directly to hyperCache™ Chipset at 66 MHz with 0 wait states • Fully registered inputs and outputs in Pipelined mode operation • 16K x 64 common I/O architecture	OCR Scan	CY82C694 128KB 66-MHz 128-pin	PDF
Untitled Abstract: No abstract text available Text: PRELIMINARY CY82C692 Pentium hyperCache™ Chipset Data-Path/Integrated Cache for h C -VX, h C -D X Solutions Features Two-bit wraparound counter supporting Intel Burst or Linear burst sequence Supports 3-1-1-1 Level 2 cache operation up to 66 MHz bus speed	OCR Scan	CY82C692 CY82C691 CY82C693 64-bit 128-KB)	PDF
EQUIVALENT cd 1031 cs Abstract: 7C1031 Text: CY7C1031 CY7C1032 PRELIM INARY 64K x 18 Synchronous Cache RAM • Direct interface with the processor and external cache controller • Asynchronous output enable • VOs capable of 33V operation • JEDEC-standard pinout • 52-pin PLCC and PQFP packaging	OCR Scan	CY7C1031 CY7C1032 66-MHz 7C1031) 7C1032) 52-pin EQUIVALENT cd 1031 cs 7C1031	PDF
Untitled Abstract: No abstract text available Text: MOSEL VITELIC V63C31321024 32K X 32 CMOS SYNCHRONOUS BURST PIPELINED SRAM PRELIMINARY Features Functional Description • ■ ■ ■ ■ ■ ■ ■ ■ The V63C31321024 is a high-speed synchro nous burst pipelined CMOS SRAM organized as 32,768 words by 32 bits that supports both ¡486/	OCR Scan	V63C31321024 100-pin 680X0/Power V63C31321024 0M02MIN.	PDF

ADVH Search Results

ADVH Datasheets Context Search

64KX32

Untitled

K7A161801M

K d998 transistor

CY7C1382DV33-200BZI

Untitled

CY7C1360C-250BGC

CY7C1325G

Transistor TT 2246

CY7C1327G

a42 a331

Untitled

WED2ZL361MSJ35BC

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adsh 13

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10EZ11

Untitled

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00Q01

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EQUIVALENT cd 1031 cs

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