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    Untitled

    Abstract: No abstract text available
    Text: SPACE ELECTRONICS INC. 8 MEGABIT EEPROM MCM GND I/O15 ADDR07 GND ADDR06 5V ADDR05 ADDR04 ADDR03 ADDR02 ADDR01 79LV0832RP ADDR00 GND 5V GND GND GND GND 5V GND GND GND GND I/O16 SPACE PRODUCTS 73 CE1 I/O17 I/O14 1 I/O18 I/O13 I/O19 I/O12 I/O20 I/O11 I/O21 I/O10


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    PDF I/O15 ADDR07 ADDR06 ADDR05 ADDR04 ADDR03 ADDR02 ADDR01 79LV0832RP ADDR00

    YMB 06

    Abstract: ADDR01
    Text: 8 MEGABIT EEPROM MCM SPACE ELECTRONICS INC. 79C0832RP GND ADCBUS35 ADDRESS 73 ADDR07 5V GND ADDR06 ADDR05 ADDR04 ADDR03 ADDR02 ADDR01 ADDR00 5V GND GND GND GND GND GND 5V GND ADCBUS36 GND GND SPACE PRODUCTS GROUP CE1 ADCBUS34 1 ADCBUS38 ADCBUS33 ADCBUS39 ADCBUS32


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    PDF ADCBUS36 ADDR00 ADDR01 ADDR02 ADDR03 ADDR04 ADDR05 ADDR06 ADDR07 ADCBUS35 YMB 06

    79C0832RP

    Abstract: No abstract text available
    Text: SPACE ELECTRONICS INC. 8 MEGABIT EEPROM MCM GND I/O15 ADDRESS CE1 73 ADDR07 GND ADDR06 5V ADDR05 ADDR04 ADDR03 79C0832RP ADDR02 ADDR01 ADDR00 GND GND 5V GND GND GND GND GND 5V GND GND I/O16 SPACE PRODUCTS I/O14 1 I/O18 I/O13 I/O19 I/O12 I/O20 I/O11 I/O21 I/O10


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    PDF I/O15 ADDR07 ADDR06 ADDR05 ADDR04 ADDR03 79C0832RP ADDR02 ADDR01 ADDR00 79C0832RP

    ADVANCED COMMUNICATION DEVICES

    Abstract: ACD80800 ACD80900 ACD82216 ACD82224 16N03 P03R
    Text: Advanced Communication Devices Corp ADVANCE INFORMATION Data Sheet: ACD82224 ACD82224 24 Ports 10/100 Fast Ethernet Switch Last Update: September 19, 2000 Please check ACD’ s website for update information before starting a design Web site: http://www.acdcorp.com


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    PDF ACD82224 Register-20 ADVANCED COMMUNICATION DEVICES ACD80800 ACD80900 ACD82216 ACD82224 16N03 P03R

    chilled water system

    Abstract: No abstract text available
    Text: Data Sheet, Revision 3 September 21, 2005 TSI-2 2k x 2k Time-Slot Interchanger 1 Introduction The last issue of this data sheet was August 31, 2005. A change history is included in Section 11 Change History on page 61. Red change bars have been installed on all text, figures, and tables that were added or changed. All changes to the text


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    PDF condit138 DS05-116STSI-3 DS05-116STSI-2) chilled water system

    IVG10

    Abstract: B08 REGULATOR
    Text: Blackfin Embedded Symmetric Multiprocessor ADSP-BF561 a FEATURES PERIPHERALS Dual symmetric 600 MHz high performance Blackfin cores 328K bytes of on-chip memory see memory information on Page 4 Each Blackfin core includes: Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,


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    PDF 16-bit 40-bit 256-ball 297-ball ADSP-BF561 IVG10 B08 REGULATOR

    Z0200045FSC

    Abstract: Z8720020FSC qpsk modulation and demodulation Z0200020FSC Z87200 Z8720045FSC single chip bpsk modulator of lower carrier freq pn qpsk 1210BH stel-2000a
    Text: PRODUCT SPECIFICATION Z Z87200 1 SPREAD-SPECTRUM TRANSCEIVER FEATURES Device Z87200 Min PN Rate* Max Data Speed Mchips Rate* (Mbps) (MHz) Package 11 2.048 20/45 100-Pin PQFP Note: *45 MHz only • Full- or Half-Duplex Operation Benefits ■ High Performance and High Reliability for Reduced


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    PDF Z87200 100-Pin Z87200 Z0200045FSC Z8720020FSC qpsk modulation and demodulation Z0200020FSC Z8720045FSC single chip bpsk modulator of lower carrier freq pn qpsk 1210BH stel-2000a

    fprog 2 schematic

    Abstract: A18E A17E HC12 M68HC12 MC68HC812A4 MC68HC812A4PV 32byte
    Text: Advance Information This document contains information on a new product. Specifications and information herein are subject to change without notice. A G R E E M E N T MC68HC812A4 N O N - D I S C L O S U R E HC12 R E Q U I R E D Order this document by MC68HC812A4/D


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    PDF MC68HC812A4 MC68HC812A4/D fprog 2 schematic A18E A17E HC12 M68HC12 MC68HC812A4 MC68HC812A4PV 32byte

    ADSP-BF526BBCZ-4AX

    Abstract: BF523 ADSP-BF522 ADSP-BF523 ADSP-BF524 ADSP-BF525 ADSP-BF526 ADSP-BF527 ADSP-BF527BBCZ-5A
    Text: Blackfin Embedded Processor ADSP-BF522/523/524/525/526/527 Preliminary Technical Data FEATURES PERIPHERALS Up to 600 MHz high-performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of


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    PDF ADSP-BF522/523/524/525/526/527 16-bit 40-bit ADSP-BF523/525/527 ADSP-BF522/524/526 289-ball 208-ball ADSP-BF526BBCZ-4AX ADSP-BF526BBCZ-4AX BF523 ADSP-BF522 ADSP-BF523 ADSP-BF524 ADSP-BF525 ADSP-BF526 ADSP-BF527 ADSP-BF527BBCZ-5A

    RXD55

    Abstract: RXD26
    Text: Hardware Design Guide June 2004 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Introduction Related Documents This document describes the hardware interfaces to Agere Systems Inc. scalable time-slot interchanger STSI-144 device. Information relevant to the use of


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    PDF STSI-144 STSI-144) DS04-230SWCH DS04-168SWCH DS04-214SWCH) RXD55 RXD26

    NHI-156XX

    Abstract: TAG 9031 15XXX NHI-15XX 56xx stanag 4007
    Text: NATIONAL HYBRID, Inc. NHi-156XX Terminals NHi-157XX Terminals Bus Controller, Remote Terminal, Bus Monitor PCI Bus And Local Bus Host Interface User's Manual Version 2007.02.24 February 2007 The information provided in this document is believed to be accurate; however, no responsibility is assumed by NATIONAL


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    PDF NHi-156XX NHi-157XX lclread15xxx NHi-15xxx //15xxx NHi-15xxx. lclwrite15xxx TAG 9031 15XXX NHI-15XX 56xx stanag 4007

    A18E

    Abstract: fprog 2 schematic MC68HC812A4CPV8 M68HC12 MC68HC812A4 MC68HC812A4PV 32byte
    Text: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. MC68HC812A4 Data Sheet M68HC12 Microcontrollers MC68HC812A4/D Rev. 6, 8/2002 MOTOROLA.COM/SEMICONDUCTORS For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.


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    PDF MC68HC812A4 M68HC12 MC68HC812A4/D A18E fprog 2 schematic MC68HC812A4CPV8 M68HC12 MC68HC812A4 MC68HC812A4PV 32byte

    TS127 08

    Abstract: RXD55 RXD01 txd45 RXD4-8 RXD35 TSI-16 RXD26 TXD38 TXD37
    Text: Advance Information May 2003 TSI-16 Time-Slot Interchanger Hardware Design Guide Introduction Related Documents This document describes the hardware interfaces to Agere Systems Inc. TSI-16 device. Information relevant to the use of the device in a board design is covered. Ball descriptions, dc electrical characteristics,


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    PDF TSI-16 DS03-124SWCH DS02-075SWCH) TS127 08 RXD55 RXD01 txd45 RXD4-8 RXD35 RXD26 TXD38 TXD37

    PF31

    Abstract: ADSP-BF561 PF29
    Text: Blackfin Embedded Symmetric Multi-Processor ADSP-BF561 High Speed Preliminary Technical Data FEATURES PERIPHERALS Up to 750 MHz Dual Symmetric High Performance Blackfin Core 328 KBytes of On-chip Memory See Memory Info on page 3 Each Blackfin Core Includes:


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    PDF ADSP-BF561 16-Bit 40-Bit 297-Ball MS-034, SpeedKBCZ-600 PF31 PF29

    Untitled

    Abstract: No abstract text available
    Text: Blackfin Embedded Symmetric Multiprocessor ADSP-BF561 FEATURES Dual symmetric 600 MHz high performance Blackfin cores 328K bytes of on-chip memory see Memory Architecture on Page 4 Each Blackfin core includes Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,


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    PDF ADSP-BF561 16-bit 40-bit 256-ball 297-ball 32-bit

    PF31

    Abstract: ADSP-BF561 B08 REGULATOR
    Text: Blackfin Embedded Symmetric Multiprocessor ADSP-BF561 a FEATURES PERIPHERALS Dual symmetric 600 MHz high performance Blackfin cores 328K bytes of on-chip memory see memory information on Page 4 Each Blackfin core includes: Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,


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    PDF ADSP-BF561 16-bit 40-bit 256-ball 297-ball D04696-0-5/06 PF31 ADSP-BF561 B08 REGULATOR

    SuperSPARC

    Abstract: Mbus master 250 slave circuit tmx390 STP1091-60
    Text: S un M icroelectronics July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus sys­


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    PDF STP1091 STP1020 STP1021 33x8k STP1091PGA-75 STP1091PGA-90 STP1020HS STP1091 SuperSPARC Mbus master 250 slave circuit tmx390 STP1091-60

    WE32100

    Abstract: ALI m7 101b WE32104
    Text: WE 32104 DMA Controller Description The WE 32104 DMA Controller DMAC is a mem ory-mapped peripheral device that performs memory-to-memory, memory fill, mem ory-to-peripheral, and peripheral-tomemory data transfers quickly and efficiently. The DMAC contains specialized hardware that


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    PDF 32-bit 133-pin 225pF) WE32100 ALI m7 101b WE32104

    Untitled

    Abstract: No abstract text available
    Text: P r o d u c t S p e c if ic a t io n Z87200 S p r e a d - S p e c t r u m T r a n s c e iv e r FEATURES Device Min PN Rate* Mchips Z87200 11 • Max Data Speed Rate* (Mbps) (MHz) 2.048 20/45 Full- or Half-Duplex Operation Package Benefits 100-Pin PQFP ■


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    PDF Z87200 100-Pin 100-Lead

    WE32101

    Abstract: we32100 tC23E oxbe
    Text: WE 32100 Microprocessor Description The WE 32100 Microprocessor CPU is a highperformance, single-chip, 32-bit central processing unit designed for efficient operation in a high-level language environment. It performs all the system address generation, control, memory access, and


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    PDF 32-bit 32-bit) 16-bit) 225pF) WE32101 we32100 tC23E oxbe

    WE32104

    Abstract: we32100 DMAC
    Text: WE 32104 DMA Controller Description The WE 32104 DMA Controller DMAC is a memory-mapped peripheral device that performs memory-to-memory, memory fill, memory-to-peripheral, and peripheral-tomemory data transfers quickly and efficiently. The DMAC contains specialized hardware that


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    PDF 32-bit 133-pin 225pF) WE32104 we32100 DMAC

    CX23035

    Abstract: No abstract text available
    Text: • CX23035 Pin Name R A03 R A02 RA01 DB01 DB02 □ 603 DB04 VD O D 805 DB06 DB07 DB08 GFS GTOP R FC K W FCK Block Diagram Pin Fu nction s Pin No. Pin name I/O Function 1 FSW S p in d le m o to r o u tp u t filte r tim e c o n s ta n t s e le c t o u tp u t.


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    PDF CX23035

    z32100

    Abstract: LK23
    Text: Zilog P ro du ct Specification January 1987 /£ > 3 0 3 3 Z32101 MEMORY MANAGEMENT UNIT DESCRIPTION T he Z32101 M emory M anagem ent U nit MMU is a 32-bit bus-structured device that provides logicalto-physical address translation, memory organization, control, and access protection for


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    PDF Z32101 32-bit Z32100 LK23

    Z180MPU

    Abstract: No abstract text available
    Text: product S p e c if ic a t io n Z80181 Z181 SAC Sm art A ccess Co n t r o ller FEATURES • Z80180 C om patible MPU Core with 1 channel of Z85C30 SCC, Z80 CTC, two 8-bit general purpose parallel ports, and two chip select signals. ■ High speed operation 10/12.5 MHz


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    PDF Z80181 100-pin Z84C30 16-bit Z180MPU