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Catalog Datasheet	MFG & Type	PDF	Document Tags
CDC5801 Abstract: CDCVF2310 Text: CDC5801 LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT SCAS682A – OCTOBER 2002 D Low Jitter Clock Multiplier by x4, x6, x8. D D D D D D D D D D D Input Frequency Range 19 MHz to 125 MHz . Supports Output Frequency From 150 MHz to 500 MHz	Original	PDF	CDC5801 SCAS682A CDC5801 CDCVF2310
12K-20MHZ Abstract: No abstract text available Text: SCAS682 • • • CDC5801 LOW JITTER CLOCK MULTIPLIER & DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT Low jitter clock multiplier by X4, X6, X8. Input frequency range 19MHZ to 135MHZ . Supports output frequency from 76 MHZ to 540MHZ Low jitter clock divider by /2, /3, /4. Input frequency range	Original	PDF	SCAS682 CDC5801 19MHZ 135MHZ) 540MHZ 75MHZ 130MHZ) 25MHZ 65MHZ 12K-20MHZ) 12K-20MHZ
CDC5801 Abstract: CDC5801DBQ CDC5801DBQR CDC5801DBQRG4 CDCVF2310 Text: CDC5801 LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT SCAS682B − OCTOBER 2002 − OCTOBER 2005 D Low Jitter Clock Multiplier by x4, x6, x8. D D D D D D D D D D D Input Frequency Range 19 MHz to 125 MHz . Supports Output Frequency	Original	PDF	CDC5801 SCAS682B CDC5801 CDC5801DBQ CDC5801DBQR CDC5801DBQRG4 CDCVF2310
AT 2005A Abstract: CDF5801 FPGA reference DCF58 TLK2521 CDC7005 CDCF5801 CDCV304 CDCVF2310 DCF5801 Text: Application Report SCAA070B – January 2004 – Revised October 2005 A General Guideline: How to Use the CDCF5801 for Phase Alignment/Adjustment Firoj Kabir. CDC/HPA	Original	PDF	SCAA070B CDCF5801 AT 2005A CDF5801 FPGA reference DCF58 TLK2521 CDC7005 CDCV304 CDCVF2310 DCF5801