RGB524
Abstract: ibm comp M5F11 IBM vga registers
Text: IBM RGB524 170/220 MHz High Performance Palette DAC Product Description Product Highlights The RGB524TM High Performance Palette DAC from IBM brings the high quality and advanced capabilities of the previous generation RGB525 to a more compact package footprint,
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Original
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RGB524TM
RGB525
RGB524
144-pin
64-bit
24-bit
64x64
RGB525,
1280x1024
ibm comp
M5F11
IBM vga registers
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Untitled
Abstract: No abstract text available
Text: RGB624/RGB624DB 1.0 Microprocessor Access As seen on th e m icroprocessor bus th e re are eight I/O addresses, selected by RS[2:0]. Two indirect schemes are used to access all of th e in te rn a l registers and arrays through th ese eight prim ary I/O addresses.
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OCR Scan
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RGB624/RGB624DB
256x8
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a6ke
Abstract: a40V c2bl B60V coy 11
Text: RGB624/RGB624DB 6.0 6 Bit Linear Palette Output The 6 B IT LI N 6 bit linear b it of the Palette Control register affects the form at of RGB color data read from the palettes and presented to the DACs in indirect color mode. It only has effect when th e color resolution is set
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OCR Scan
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RGB624/RGB624DB
a6ke
a40V
c2bl
B60V
coy 11
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Untitled
Abstract: No abstract text available
Text: RGB624/RGB624DB Appendix A.O RGB624, RGB624DB Comparison T h e R G B 6 2 4 D B is a s u p e r s e t o f th e R G B 6 2 4 t h a t a d d s th e 16 B P P d o u b le b u ffe r o p e ra tio n . T h e tw o p ro d u c ts a re p in a n d re g is te r c o m p a tib le a n d a re id e n tic a l in a ll
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RGB624/RGB624DB
RGB624,
RGB624DB
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CAPACITOR 64 680 4J
Abstract: CAPACITOR 62 680 4J PIX203 IX533 RGB624
Text: RGB624/RGB624DB 16.0 Pin Descriptions Table 16. Pin Descriptions Signal Typ e D escription Pin s Clocks and Clock Controls REFC LK 1 80 Reference Clock. A fixed frequency of 2 M H z to 100 M Hz applied to th is pin provides the reference clock for the programmable pixel and system clock
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OCR Scan
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RGB624/RGB624DB
P1X1171
PIXL63
XI581
PIXJ381
CAPACITOR 64 680 4J
CAPACITOR 62 680 4J
PIX203
IX533
RGB624
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0X0047
Abstract: RGB624 GMPM2-B112RCBSXU.110
Text: RGB624/RGB624DB 14.0 Internal Register - Summary RS[2:0] Index R /W Reset Value 110 0x0015 / 0x08 SYSCLKN S ystem P L L Reference D iv id e r 110 0x0016 / 0x41 SYSCLK M (S ystem P L L VCO D iv id e r) 110 0x0017 110 0x0018 R egister Nam e 110 0x00190x001f
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OCR Scan
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RGB624/RGB624DB
0x0015
0x0090
0x0091
0x0092
0x009f
0x00a1
0x00a2
0x00a3
0x00a4
0X0047
RGB624
GMPM2-B112RCBSXU.110
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RGB624
Abstract: cursor
Text: RGB624/RGB624DB 9.0 Controls 9.1 Blank and Border Control The B L A N K and B O R DER/O E signals control the way in which data is presented to the DACs. These control signals are used to determ ine when pixel data is valid, when the border color is to be displayed, where the cur
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OCR Scan
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RGB624/RGB624DB
RGB526/RGB526DB
RGB51x
RGB52x
RGB624
cursor
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37RGB624cf
Abstract: RGB624 37RGB624
Text: RGB624/RGB624DB 19.0 Package Information % 20.0 Ordering Information Table 24. Part Numbers Product Part Number Speed IBM RGB624 CF 17 170 MHz IBM RGB624 CF 22 220 MHz IBM RGB624 DB 17 170 MHz IBM RGB624 DB 22 220 MHz RGB624 RGB624DB October 9 , 1995
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OCR Scan
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RGB624/RGB624DB
RGB624
37RGB624
RGB624DB
37RGB624cf
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RGB624
Abstract: No abstract text available
Text: RGB624/RGB624DB 7.0 Color Space Conversion The internal color space converter takes pixels with Y, U, and V values of 8 bits each and converts them to pix els of R, G, and B values of 8 bits each, using the follow ing equations: 7.2 Coefficients The constants K1 - K4 are 8 bit values are can be pro
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OCR Scan
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RGB624/RGB624DB
RGB624/RGB624DB
RGB624
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FS10J
Abstract: No abstract text available
Text: RGB624/RGB624DB 15.0 Register Descriptions Pixel Mask / 15.1 7 6 The direct access registers are addressed using RS 2:0] inputs. RS[2:0]: 010 Access: Read/Write Bits 7 - 0 6 5 4 3 2 1 0 > W R IT E A d dress RS[2:0]: 000 Access: Read/Write Pow er on Value: Undefined
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RGB624/RGB624DB
FS10J
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b624
Abstract: No abstract text available
Text: RGB624/RGB624DB 21.0 Change Summary _ Table 25. Summary of Changes Date Changes 02/06/95 1. 10/09/95 T h is re visio n adds th e R G B 624D B p ro d u ct; th e d o cu m e n t becomes a co m b in e d R G B 624/R G B 624D B d a ta
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RGB624/RGB624DB
624/R
B624D
B624DB.
B526/R
B526D
RGB524"
b624
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DF0001
Abstract: RGB624
Text: RGB624/RGB624DB D.O PLL Compatibility Programming REF DIV COUNT R e fe re n c e D ivide C o u n t This The RG B51x and RGB52x products all have a program mable P L L for generating a pixel clock, and the RG B524 and RG B528 have a second P L L for driving a "S Y S C L K "
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OCR Scan
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RGB624/RGB624DB
RGB52x
RGB51x/RGB52x"
B624/RG
B624D
RGB624/RG
0x0014)
DF0001
RGB624
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Untitled
Abstract: No abstract text available
Text: RGB624/RGB624DB 12.0 Power Management 12.3 The following registers are used to control power dissipation: Most of the digital logic power dissipation occurs as a result of clocking. The IC L K PWR, SCLK PWR, D D O T PWR, and S YN C PW R bits of the Power Management
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OCR Scan
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RGB624/RGB624DB
0x0005)
0x0002)
0x0003)
0x0070)
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RGB624
Abstract: No abstract text available
Text: RGB624/RGB624DB E.O Switching Into VGA Mode The R G B624/RGB624DB has two fundam ental modes of operation which depend on the input pixel port selected, VGA or V R A M . The port is selected w ith the "PORT SEL” b it bit 0 of Miscellaneous Control 2 register.
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OCR Scan
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RGB624/RGB624DB
RGB624/RGB624DB
RGB513,
RGB514,
RGB525
RGB624
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Untitled
Abstract: No abstract text available
Text: RGB624/RGB624DB 1.0 Microprocessor Access A s seen on the m icroprocessor b u s there are eight I/O addresses, selected by RS[2:0]. T w o indirect schem es are used to access all of the internal registers and a rra ys th ro u g h these eight p rim a ry I/O addresses.
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RGB624/RGB624DB
0x0100.
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RGB624
Abstract: No abstract text available
Text: RGB624/RGB624DB 17.0 Electrical and Timing Specifications Table 18. Recommended Operating Conditions 170 M H z P aram eter 220 M H z Symbol U n its M in . M ax. M in . M ax . VDD, DACVDD, PLLVDD 3.0 3.6 3.0 3.6 Volts Case Temperature TC 100 100 C DAC Output Load
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RGB624/RGB624DB
624/R
RGB624
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RGB624
Abstract: C2-M3
Text: RGB624/RGB624DB 2.0 Clocking 2.1 Clock Generators T h ere are tw o on-board clock generators: p ixe l clock and system clock SYSC LK . Each clock g e n e ra to r uses a separate p ro gram m able phase locked loop (P LL). T h is causes th e S Y S C LK s ta rt up frequency to be
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OCR Scan
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RGB624/RGB624DB
0x008e
0x008c
0x008d
RGB624
C2-M3
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RS-343-A
Abstract: ef927 RS-343A RGB624
Text: RGB624/RGB624DB 18.0 Video Waveforms WHITE BLACK BLANK SYNC Table 22. Composite Video Output Waveform D o u b ly te rm in a te d 75 ohms, R R E F= 698 ohm s Sync No Pedestal V alu e No No IR E W H ITE Yes Yes mA V 18.65 0.70 100 IR E i No mA V 19.05 0.714
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RGB624/RGB624DB
RS-343A
RS-343-A
ef927
RGB624
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PIX-1400
Abstract: No abstract text available
Text: RGB624/RGB624DB 3.0 Modes of Operation Pixel data can come from the V G A port or the VRAM pixel port, as selected by the P O R T S E L bit of the M is cellaneous Control 2 register. If the V R A M pixel port is selected, the pixel format can be 4 B P P bits per pixel , 8 BPP, 15/16 BPP, 24 B P P
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OCR Scan
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RGB624/RGB624DB
PIX-1400
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PDF
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RGB524
Abstract: RGB526/RGB526DB
Text: RGB526/RGB526DB 1.0 Microprocessor Access As seen on th e m icroprocessor bus th e re are eight I/O addresses, selected by RS[2:0]. Two indirect schemes are used to access all of th e in te rn a l registers and arrays through th ese eight prim ary I/O addresses.
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OCR Scan
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RGB526/RGB526DB
256x8
RGB524
RGB526/RGB526DB
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Untitled
Abstract: No abstract text available
Text: RGB526/RGB526DB N gives finer control in program m ing for the desired output frequencies, and allows the in ternal operat ing points of the P L L s to be fine tuned. Appendix A.O RGB526, RGB526DB Comparison The R G B 526D B is a su perset of th e R G B 526 th a t adds
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RGB526/RGB526DB
RGB526,
RGB526DB
0x000d
B526D
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37rgb
Abstract: rgb525 RGB524 pix15
Text: RGB524 1.0 Microprocessor Access As seen on the microprocessor bus there are eight I/O addresses, selected by RS[2:0], Two indirect schemes are used to access all of the internal registers and arrays through these eight primary I/O addresses. The first scheme is standard VGA, and operates when
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OCR Scan
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RGB524
256x8
0x0002,
RGB524/RGB528
0x0000)
IBM37-RGB524-CF-17C
IBM37-RGB524-CF-22C
IBM37-RGB524-CF-17C-A
IBM37-RGB524-CF-22C-A
37rgb
rgb525
pix15
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