P1750A Search Results

pace1750

Abstract: 1750a PACE1750AE
Contextual Info: P1750AE/SOS SINGLE CHIP, 30MHz, ENHANCED SPACE PROCESSOR FEATURES Implements the MIL-STD-1750A Instruction Set Architecture Single Chip MIL-STD-1750AE Processor Form-Fit-Functionally Compatible with the P1750A CMOS Processor DAIS Instruction Mix Execution Performance

Contextual Info: P1750A/SOS SINGLE CHIP, 30MHz, CMOS/SOS SPACE PROCESSOR FEATURES • Implements the MIL-STD-1750A Instruction Set Architecture ■ Built-In Self Test ■ 24 User Accessible Registers ■ CMOS/SOS Processor with 32 and 48-Bit Floating Point Arithmetic ■ Single 5V ± 10% Power Supply

Contextual Info: P1750A/SOS SINGLE CHIP, 20MHz to 30MHz, CMOS/SOS SPACE PROCESSOR FEATURES Implements the MIL-STD-1750A Instruction Set Architecture Built-In Self Test 24 User Accessible Registers CMOS/SOS Processor with 32 and 48-Bit Floating Point Arithmetic Single 5V ± 10% Power Supply

pace1750

Abstract: as3 SMD Transistor PACE1750A
Contextual Info: P1750A/SOS SINGLE CHIP, 20MHz to 30MHz, CMOS/SOS SPACE PROCESSOR FEATURES Implements the MIL-STD-1750A Instruction Set Architecture Built-In Self Test 24 User Accessible Registers CMOS/SOS Processor with 32 and 48-Bit Floating Point Arithmetic Single 5V ± 10% Power Supply

Combo Driver

Abstract: 1750a 1F41 P150A P1753 PACE1754 P1750A ANP16-001
Contextual Info: APPLICATION NOTE PACE P1754 PIC SYSTEM TEST The PACE1754 PIC chip provides the system designer with a system test which may be run at power-up if enabled. This test is very useful for establishing the functionality of the P1750A/AE CPUs, P1753 COMBO, and the P1754 PIC

dsp radiation tolerance

Contextual Info: P1750AE/SOS SINGLE CHIP, 30MHz, ENHANCED SPACE PROCESSOR FEATURES Implements the MIL-STD-1750A Instruction Set Architecture Single Chip MIL-STD-1750AE Processor Form-Fit-Functionally Compatible with the P1750A CMOS Processor DAIS Instruction Mix Execution Performance

Contextual Info: PACE1750AE SINGLE CHIP, 40MHz, ENHANCED CMOS 16-BIT PROCESSOR FEATURES • Im plem ents th e M IL-STD-1750A Instruction Set Architecture ■ Single Chip PACE Technology CM OS 16-Bit Processor with 32 and 48-Bit Floating Point Arithm etic ■ Form-Fit-Functionally Com patible with the P1750A

P1757

Abstract: pace1750 9F51 1F42 PACE P1757M PACE1757ME P1750A 4f05 mil-std-1750a
Contextual Info: PACE1757M/ME COMPLETE EMBEDDED CPU SUBSYSTEM FEATURES Implements complete MIL-STD-1750A ISA including optional MMU, MFSR, and BPU functions. Two throughput options: P1757M 2.5MIPS USAF Dais Mix Inc.Flt.Pt. @40 MHz P1757ME 3.6MIPS USAF Dais Mix (Inc.Flt.Pt.)@40 MHz

Contextual Info: PACE1754/SOS PROCESSOR INTERFACE CIRCUIT PIC CMOS/SOS SPACE PROCESSOR MICROPERIPHERAL FEATURES The PACE1754 (PIC) is a support chip for the PACE1750A/AE Processors. It eliminates the SSI/MSI Logic and external system functions required in typical 1750A implementations.

diode sk 4f1/ 02

Abstract: diode sk 4f1 pace1750 pace1750a F9450 diode sk 4f1/ 10 PACE1750AE P1750A MJ015 mil-std-1750a
Contextual Info: PACE1750AE SINGLE CHIP, 40MHz, ENHANCED CMOS 16-BIT PROCESSOR IP 1 F 8 E L M D IN M Y FEATURES — Parametric Memory Inner-Dot Products for Matrix Computations Up To 64K. — Fast Polynomial expansion algorithm. — Fast context switching with instruction to block

IN4118

Abstract: 1750AE pace1750 PACE1750A PACE1750AE MILSTD-1750A ANP-16 MN1631
Contextual Info: APPLICATION NOTE PACE1750AE BUILT-IN FUNCTIONS About This Note This application brief is intended to explain and demonstrate the use of the special functions that are built into the PACE1750AE processor. These powerful Built-In Functions BIFs are above and beyond the capabilities of the MILSTD-1750A instruction set, but are allowed by MIL-STD-1750A as options to enhance the performance of 1750A

1f58

Abstract: programmable pipeline microcode memory
Contextual Info: PACE1754/SOS PROCESSOR INTERFACE CIRCUIT PIC CMOS/SOS SPACE PROCESSOR MICROPERIPHERAL FEATURES • The PACE1754 (PIC) Is a support chip for the PACE1750A/AE Processor. It eliminates the SSI/ MSI Logic and external system functions required in typical 1750A implementations.

P1750A performance

Abstract: 5962-8766501TX P1750A20PGM P1750A-20PGMB
Contextual Info: PACE1750A SINGLE CHIP, 40MHz, CMOS 16-BIT PROCESSOR - • : — ; : FEATURES ■ Implements the MIL-STD-1750A Instruction Set Architecture ■ 20,30 and 40 MHz operation over the Military Temperature Range ■ Single Chip PACE Technology CMOS 16-Bit Processor with 32 and 48-Bit Floating Point

Contextual Info: PACE 1757M/ME p r e l im in a r y COMPLETE EMBEDDED CPU SUBSYSTEM -FFATURES Implements complete MIL-STD-1750A ISA Including optional MMU, MFSR, and BPU functions. • Programmable address wait states.

as3 SMD Transistor

Abstract: IB435 AK010 mil-std-1750 PACE1750A PACE1750AE P1750A mil-std-1750a smd ak3
Contextual Info: PACE1750AE SINGLE CHIP, 20MHz to 40MHz, ENHANCED CMOS 16-BIT PROCESSOR FEATURES Implements the MIL-STD-1750A Instruction Set Architecture Single Chip PACE TechnologyTM CMOS 16-Bit Processor with 32 and 48-Bit Floating Point Arithmetic Form-Fit-Functionally Compatible with the

MIL-STD-1750

Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED A Added device type 04. Technical changes were implemented. Editorial changes throughout. 92-05-06 Monica L. Poelking B Added device types 05, 06, and 07. Technical changes to table I. Editorial changes throughout.

Contextual Info: PACE1750AE SINGLE CHIP, 20MHz to 40MHz, ENHANCED CMOS 16-BIT PROCESSOR FEATURES Implements the MIL-STD-1750A Instruction Set Architecture Single Chip PACE TechnologyTM CMOS 16-Bit Processor with 32 and 48-Bit Floating Point Arithmetic Form-Fit-Functionally Compatible with the

Contextual Info: PACE1757M/ME COMPLETE EMBEDDED CPU SUBSYSTEM FEATURES Implements complete MIL-STD-1750A ISA including optional MMU, MFSR, and BPU functions. Two throughput options: P1757M 2.5MIPS USAF Dais Mix Inc.Flt.Pt. @40 MHz P1757ME 3.6MIPS USAF Dais Mix (Inc.Flt.Pt.)@40 MHz

Contextual Info: PACE 1757M/ME COMPLETE EMBEDDED CPU SUBSYSTEM 4 -FFATURES Implements complete MIL-STD-1750A ISA Including optional MMU, MFSR, and BPU functions. • Programmable address wait states. • Sixteen levels of interrupts are provided per MIL-STD1750A. Interrupts can be either edge- or level-sensitive

Contextual Info: PACE1750AE SINGLE CHIP, 40MHz, ENHANCED CMOS 16-BIT PROCESSOR 4 -

Contextual Info: PACE1750AE SINGLE CHIP, 40MHz, ENHANCED CMOS 16-BIT PROCESSOR FEATURES — Parametric Memory Inner-Dot Products for Matrix Computations Up To 64K. — Fast Polynomial expansion algorithm. — Fast context switching with instruction to block move up to 16 new mapping memory page

Contextual Info: PACE1750A SINGLE CHIP, 40MHz, CMOS 16-BIT PROCESSOR FEATURES • Implements the MIL-STD-1750A Instruction Set Architecture ■ 20, 30 and 40 MHz operation over the Military Temperature Range ■ Single Chip PACE Technology CMOS 16-Blt Processor with 32 and 48-Blt Floating Point

HIT 7070

Abstract: k1757
Contextual Info: PERFORMANCE SEMI CONDUCTOR SOE D • 70bBST7 000175b 32T ip PACE 1757M/ME PREÜMl COMPLETE EMBEDDED CPU SUBSYSTEM FEATURES Programmable address wait states. Implements complete MIL-STD-1750A ISA Including optional MMU, MFSR, and BPU functions. Sixteen levels of interrupts are provided per MIL-STD1750A. Interrupts can be either edge- or level-sensitive.

1750A processor architecture

Abstract: PACE1750A KTC AS1-708N
Contextual Info: PACE1750AE SINGLE CHIP, 40MHz, ENHANCED CMOS 16-BIT PROCESSOR 4 - — FEATURES — - — • Implements the MIL-STD-1750A Instruction Set Architecture ■ Single Chip PACE Technology CMOS 16-BH Processor with 32 and 48-Bit Floating Point