MT9075
Abstract: E1 to ethernet converter circuit "network interface cards"
Text: MT90210 Multi-Channel Parallel Access Circuit Features & Benefits Guide September 14, 1998 Revision 1.0 MT90210 Features & Benefits Guide Product Summary The MT90210 is a Multi-rate Parallel Access Circuit, that allows streaming of DS0 and Nx64Kbps streams between an isochronous serial TDM bus and a
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MT90210
Nx64Kbps
MT90210
Nx64Kb/s
MT8980
MT9075
E1 to ethernet converter circuit
"network interface cards"
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ATM circuit diagram
Abstract: MT90220 MT9045 MT90503 MT90528 MT9072 MT9076 VTOA-0078
Text: AAL1 SAR MT90503 Network Connectivity The MT90503 is a multi-channel ATM Adaptation Layer 1 AAL1 segmentation and reassembly (SAR) device that interfaces serial stream voice and data traffic from the TDM bus to the ATM network. The device provides the industry’s
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MT90503
MT90503
155Mbps
622Mbit/s
503-pin
PP5670
ATM circuit diagram
MT90220
MT9045
MT90528
MT9072
MT9076
VTOA-0078
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Untitled
Abstract: No abstract text available
Text: Rev: 032609 DS34S101, DS34S102, DS34S104, DS34S108 Single/Dual/Quad/Octal TDM-over-Packet Chip General Description These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial
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DS34S101,
DS34S102,
DS34S104,
DS34S108
823/G
DS34S10x
DS34S101
DS34S102
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ATM circuit diagram
Abstract: MT9072 MT9076 MT90220 MT9045 MT90503 MT90528
Text: AAL1 SAR Network Connectivity MT90503 Highest Integration The MT90503 is a multi-channel ATM Adaptation Layer 1 AAL1 segmentation and reassembly (SAR) device that interfaces serial stream voice and data traffic from the TDM bus to the ATM network. The device provides the industry’s highest integration—
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MT90503
MT90503
155Mbps
503-pin
MT90220/1
MT9045
MT9072
PP5670
ATM circuit diagram
MT9076
MT90220
MT90528
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RESREF
Abstract: DS34T108 MDIO MDC
Text: ABRIDGED DATA SHEET Rev: 121407 DS34T101/DS34T102/DS34T104/DS34T108 Single/Dual/Quad/Octal TDM-Over-Packet Chip General Description The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be
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DS34T101/DS34T102/DS34T104/DS34T108
DS34T108
823/G
DS34S108,
DS34S104,
DS34S102,
DS34S101.
RESREF
MDIO MDC
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Untitled
Abstract: No abstract text available
Text: Rev: 032609 DS34S101, DS34S102, DS34S104, DS34S108 Single/Dual/Quad/Octal TDM-over-Packet Chip General Description These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial
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DS34S101,
DS34S102,
DS34S104,
DS34S108
DS34S101
DS34S102
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RJ48X
Abstract: USOC RJ48C TR54016 rate-based ABR modem rate-based traffic control IA-64
Text: D E V E L O P E R ’ S I N T E R F A C E G U I D E F O R I A - 6 4 S E R V E R S DIG64 Technical Whitepaper: IA-64 Server Network Communications Solutions Intel Corporation January 2000 THIS DOCUMENT IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER,
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DIG64
IA-64
RJ48X
USOC
RJ48C
TR54016
rate-based ABR modem
rate-based traffic control
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RLOF 100
Abstract: DS34t108 TDM8
Text: ABRIDGED DATA SHEET Rev: 072707 DS34T101/DS34T102/DS34T104/DS34T108 Single/Dual/Quad/Octal TDM-Over-Packet Chip General Description 3 The IETF PWE SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be
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DS34T101/DS34T102/DS34T104/DS34T108
DS34T108
823/G
DS34T101/DS34T102/DS34T104/DS34T108
RLOF 100
TDM8
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BFAP20
Abstract: samsung ltcc G.SHDSL Industry Single-Chip VTSA7 447h LQ13 tag 9018 LM 205h 276 741h EoPDH
Text: Rev: 063008 DS33X162/DS33X161/DS33X82/DS33X81/ DS33X42/DS33X41/DS33X11/DS33W41/DS33W11 Ethernet Over PDH Mapping Devices General Description The DS33X162 family of semiconductor devices extend 10/100/1000Mbps Ethernet LAN segments by encapsulating MAC frames in GFP-F, HDLC, cHDLC,
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DS33X162/DS33X161/DS33X82/DS33X81/
DS33X42/DS33X41/DS33X11/DS33W41/DS33W11
DS33X162
10/100/1000Mbps
52Mbps
35/Optical.
DS33W11
DS33W41,
DS33X41,
DS33X42,
BFAP20
samsung ltcc
G.SHDSL Industry Single-Chip
VTSA7
447h
LQ13
tag 9018
LM 205h
276 741h
EoPDH
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DS34T104GN
Abstract: 3216 footprint IPC TDM8 DS34T101GN DS34T102GN DS34T104 DS34T108GN 7U22 DS34T10x
Text: Rev: 072707 DS34T101/DS34T102/DS34T104/DS34T108 Single/Dual/Quad/Octal TDM-Over-Packet Chip General Description 3 The IETF PWE SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be transported transparently through a switched IP or
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DS34T101/DS34T102/DS34T104/DS34T108
DS34T108
823/G
DS34T104GN
3216 footprint IPC
TDM8
DS34T101GN
DS34T102GN
DS34T104
DS34T108GN
7U22
DS34T10x
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diode CH9d
Abstract: CH7C diode CH8C diode diode ch6b rg703 Diode TS21C diode code eb13 RFC-5087 10407C 2125S
Text: 19-4835; 8/09 DS34T101, DS34T102, DS34T104, DS34T108 Single/Dual/Quad/Octal TDM-over-Packet Chip General Description These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial
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DS34T101,
DS34T102,
DS34T104,
DS34T108
823/G
DS34T108.
DS34T104.
diode CH9d
CH7C diode
CH8C diode
diode ch6b
rg703 Diode
TS21C
diode code eb13
RFC-5087
10407C
2125S
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Untitled
Abstract: No abstract text available
Text: ABRIDGED DATA SHEET Rev: 072707 DS34T101/DS34T102/DS34T104/DS34T108 Single/Dual/Quad/Octal TDM-Over-Packet Chip General Description The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be
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DS34T101/DS34T102/DS34T104/DS34T108
DS34T108
823/G
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MT90520
Abstract: MT90528 ATM circuit diagram
Text: SEGMENTATION & REASSEMBLY SAR PRODUCT OVERVIEW The MT90520 and MT90528 are AAL1 (ATM Adaptation Layer 1) segmentation and reassembly (SAR) devices designed to optimize performance and cost efficiency of TDM-to-ATM conversion applications. The devices are the first AAL1 SARs with on-chip per-port PLLs that provide a total
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MT90520
MT90528
MS5947
ATM circuit diagram
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Untitled
Abstract: No abstract text available
Text: Rev: 012108 DS33X162/DS33X161/DS33X82/DS33X81/ DS33X42/DS33X41/DS33X11/DS33W41/DS33W11 Ethernet Over PDH Mapping Devices General Description The DS33X162 family of semiconductor devices extend 10/100/1000Mbps Ethernet LAN segments by encapsulating MAC frames in GFP-F, HDLC, cHDLC,
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DS33X162/DS33X161/DS33X82/DS33X81/
DS33X42/DS33X41/DS33X11/DS33W41/DS33W11
DS33X162
10/100/1000Mbps
52Mbps
35/Optical.
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
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Untitled
Abstract: No abstract text available
Text: Rev: 063008 DS3 3 X 1 6 2 /DS3 3 X 1 6 1 /DS3 3 X 8 2 /DS3 3 X 8 1 / DS3 3 X 4 2 /DS3 3 X 4 1 /DS3 3 X 1 1 /DS3 3 W4 1 /DS3 3 W1 1 Et he r ne t Ove r PDH M a pping Devic e s Ge ne ra l De sc ript ion The DS33X162 family of semiconductor devices extend 10/100/1000Mbps Ethernet LAN segments by
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DS33X162
10/100/1000Mbps
52Mbps
35/Optical.
DS33W11
DS33W41,
DS33X41,
DS33X42,
DS33X82,
DS33X161
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CRC-10
Abstract: MXT3010 MXT3020-C MXT3020-C33 MXT3020-C40 MXT3020-C60 multiplexing e1 frame to e3 frame
Text: M X T 3 0 2 0 Circuit Coprocessor for ATM Typical Applications WAN access “common card” services • AAL1-SDT, AAL1-UDT, AAL2, AAL5 • Inverse Multiplexing for ATM IMA • Cell Relay (T1/E1 UNI) • Frame Relay with external hardware • Circuit Emulation
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MXT3020s
MXT3010
MXT3020
MXT3020
to3020-C33:
379mA
40MHz,
MXT3020:
CRC-10
MXT3010
MXT3020-C
MXT3020-C33
MXT3020-C40
MXT3020-C60
multiplexing e1 frame to e3 frame
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e1 E2 e3 liu transceiver
Abstract: No abstract text available
Text: PRELIMINARY-SUBJECT TO CHANGE ABRIDGED DATA SHEET Rev: 091407 DS34S101//DS34S102/DS34S104/DS34S108 Single/Dual/Quad/Octal TDM-Over-Packet Transport Devices General Description The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34S108 allows up to eight T1/E1
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DS34S108
823/G
DS34S101/DS34S102/DS34S104/DS34S108
e1 E2 e3 liu transceiver
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samsung ltcc
Abstract: No abstract text available
Text: PRELIMINARY Rev: 060607 DS33X162/DS33X161/DS33X82/DS33X81/ DS33X42/DS33X41/DS33X11/DS33W41/DS33W11 Ethernet Over PDH Mapping Devices General Description The DS33X162 family of semiconductor devices extend 10/100/1000Mbps Ethernet LAN segments by encapsulating MAC frames in GFP-F, HDLC, cHDLC,
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DS33X162/DS33X161/DS33X82/DS33X81/
DS33X42/DS33X41/DS33X11/DS33W41/DS33W11
200ms
256Mb,
125MHz
DS33X162
deviX81/X42/X41/X11/W41/W11
144-Ball
56-G6008-003)
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
samsung ltcc
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Untitled
Abstract: No abstract text available
Text: Rev: 060607 DS33X162/DS33X161/DS33X82/DS33X81/ DS33X42/DS33X41/DS33X11/DS33W41/DS33W11 Ethernet Over PDH Mapping Devices General Description ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Y ♦ ♦ 10/100/1000 IEEE 802.3 MAC MII/RMII/GMII with Autonegotiation and Flow Control
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DS33X162/DS33X161/DS33X82/DS33X81/
DS33X42/DS33X41/DS33X11/DS33W41/DS33W11
200ms
256Mb,
125MHz
144-Ball
56-G6008-003)
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
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Untitled
Abstract: No abstract text available
Text: ABRIDGED DATA SHEET Rev: 040108 DS34S101//DS34S102/DS34S104/DS34S108 Single/Dual/Quad/Octal TDM-Over-Packet Transport Devices General Description The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC RFC-compliant DS34S108 allows up to eight T1/E1 links or frame-based serial HDLC links to be
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DS34S101//DS34S102/DS34S104/DS34S108
32-Bit
16-Bit
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Ee 19c transformer
Abstract: PCF7 sace e3 sace e2 i386ex rj48 to db9 VG96 386EX 1N4148 and/pcf7 FALC54
Text: ICs for Communications Evaluation System for Interworking Element IWE8 EASY4220 Version 1.1 with PXB 4220 IWE8 Version 1.1 PEB 2254 FALC54 Version 1.3 Tool Description 06.97 DS 1 EASY4220 Revision History: Current Version: 06.97 Previous Version: None Page
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EASY4220
FALC54
EASY4220
Ee 19c transformer
PCF7
sace e3
sace e2
i386ex
rj48 to db9
VG96 386EX
1N4148
and/pcf7
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MT9045
Abstract: MT90520 MT90528 MT9072 MT9076
Text: AAL1 SAR Network Connectivity MT90520/28 Complimentary Products SARs, IMAs, Framers, Digital PLLs, TDM to IP processors Reduced Board Space & System Cost On-chip per-port PLLs synchronize inputs to different network clocks, eliminating up to four external framers,
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MT90520/28
MT90520
MT90528
PP5834
MT9045
MT9072
MT9076
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DS34T101
Abstract: D2048 DS34S101 DS34S102 DS34T104 DS34T101GN DS34T102GN DS34T104GN DS34T108GN RFC4553
Text: ABRIDGED DATA SHEET Rev: 042608 DS34T101/DS34T102/DS34T104/DS34T108 Single/Dual/Quad/Octal TDM-Over-Packet Chip General Description The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be
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DS34T101/DS34T102/DS34T104/DS34T108
DS34T108
823/G
preS108,
DS34S104,
DS34S102,
DS34S101.
DS34T102,
DS34T104
DS34T101
D2048
DS34S101
DS34S102
DS34T101GN
DS34T102GN
DS34T104GN
DS34T108GN
RFC4553
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