EP9100
Abstract: EP9122 EP9108 EP9109 EP9110 EP9111 EP9112 EP9113 EP9114 EP9129
Text: 28 Pin SMD 5 Tap TTL Compatible Active Delay Lines ELECTRONICS INC. EP9100 to EP9129 & EP9100-RC to EP9129-RC Add “-RC” after part number for RoHS Compliant J-Lead Part Number EP9100 -RC EP9101(-RC) EP9102(-RC) EP9103(-RC) EP9104(-RC) EP9105(-RC) EP9106(-RC)
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EP9100
EP9129
EP9100-RC
EP9129-RC
EP9101
EP9102
EP9103
EP9104
EP9105
EP9122
EP9108
EP9109
EP9110
EP9111
EP9112
EP9113
EP9114
EP9129
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Untitled
Abstract: No abstract text available
Text: Classic EPLD Family January 1998, ver. 4 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with advanced, non-volatile EPROM configuration elements
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Untitled
Abstract: No abstract text available
Text: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines Delays are ±5% or ±2 nS† Tap Total 5, 10, 15, 20 6, 12, 18, 24 7, 14, 21, 28 8, 16, 24, 32 9, 18, 27, 36 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45, 60 J-Lead P/N 25 30 35 40 45 50 60 75 †Whichever is greater.
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EP9100
EP9101
EP9102
EP9103
EP9104
EP9105
EP9106
EP9107
EP9115
EP9116
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ep600i
Abstract: EP1800I EP610ILI-12 altera ep610 altera EP1810 EP1800 altera ep900i
Text: Classic EPLD Family June 1996, ver. 3 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of up to 900 usable gates see Table 1 Device erasure and reprogramming with advanced, non-volatile EPROM configuration elements
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EP910dm
Abstract: EP910PC-30 EP910DC-40 EP1810LC-35 EP1810LC-20 EP610PC-15 Programming EP610DI-30 EP910JI-35 EP610IDC25 EP610SC-15
Text: Classic EPLD Family May 1999, ver. 5 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with non-volatile EPROM configuration elements
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EP610LC-15
EP610LC-25
EP610ILI-12
EP610PC-15
EP610PI-30
EP910dm
EP910PC-30
EP910DC-40
EP1810LC-35
EP1810LC-20
EP610PC-15 Programming
EP610DI-30
EP910JI-35
EP610IDC25
EP610SC-15
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PDF
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Altera EP1810
Abstract: EP1810 EP600I EP610 EP610-15 EP610-20 EP910 EP610 "pin compatible"
Text: Classic EPLD Family June 1996, ver. 3 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of up to 900 usable gates see Table 1 Device erasure and reprogramming with advanced, non-volatile EPROM configuration elements
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ep910 programmer
Abstract: EP610 EP610-15 48-macrocell EP1810 EP610-20 EP610-25 EP610-30 EP910 ep610 application
Text: Classic EPLD Family May 1999, ver. 5 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with non-volatile EPROM configuration elements
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EP-912
Abstract: EP9100
Text: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines J-Lead P/N Delays are ±5% or ±2 nS Tap Total 5, 10, 15, 20 6, 12, 18, 24 7 ,1 4,2 1 ,2 8 8, 16,24,32 9, 18, 27,36 10,20, 30,40 12, 24, 36, 48 15,30, 45,60 EP9100 EP9101 EP9102 EP9103 EP9104 EP9105 EP9106
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EP9100
EP9101
EP9102
EP9103
EP9104
EP9105
EP9106
EP9107
EP9115
EP9116
EP-912
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PDF
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Untitled
Abstract: No abstract text available
Text: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines J-Lead P/N Delays are ±5% or ±2 nSt Tap Total 5, 10, 15, 20 6 , 12, 18, 24 7 ,1 4 ,2 1 ,2 8 8 ,1 6 ,2 4 , 32 9, 18, 27, 36 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45, 60 EP9100 EP9101 EP9102 EP9103 EP9104
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EP9100
EP9101
EP9102
EP9103
EP9104
EP9105
EP9106
EP9107
EP9115
EP9116
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PDF
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EP910T
Abstract: altera EP910 EP910-T
Text: EP910T EPLD Features □ □ a □ □ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD = 30 ns Counter frequencies up to 33 MHz Pipelined data rates up to 41 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs Pin-, function-, and programming file-compatible with Altera's EP910
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EP910T
24-macrocell
EP910
EP910A
44-pin
40-pin
ALTED001
altera EP910
EP910-T
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PDF
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EP9122
Abstract: circuit ep9100 smd 57b EP9100 EP9101 EP9102 EP9108 EP9109 EP9110 EP9115
Text: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines Delays are ±5% or +2 nSt Tap Total 5, 10, 15, 20 6, 12, 18, 24 7, 14, 21, 28 8, 16, 24, 32 9, 18, 27, 36 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45, 60 J-Lead P/N 25 30 35 40 45 50 60 75 t Whichever is greater.
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EP9100
EP9115
EP9108
EP9123
EP9101
EP9116
EP9109
EP9124
EP9102
EP9117
EP9122
circuit ep9100
smd 57b
EP9110
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PDF
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EP610-25
Abstract: programmer EPLD EP1810 EP610 EP910 ep910 programmer QLCC 24 EP6101-10
Text: Classic E P L D F a m ily Ja n u a ry 1098, ve r 4 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ C om plete device fam ily w ith logic densities o f 300 to 9 X usable gates (see Table 1) D evice e ra su re an d reprogram m ing w ith advanced, non-volatile
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of300
EP1810
68-pin
EP610-25
programmer EPLD
EP610
EP910
ep910 programmer
QLCC 24
EP6101-10
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PDF
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EP910
Abstract: EP910-35 FLIPFLOP SCHEMATIC 10KHZ 74HC EP910-30 EP910-40 EP910A
Text: FEATURES GENERAL DESCRIPTION • High density over 900 gates replacem ent for T T L and 74HC. • Advanced C M O S E P R O M tech n olo gy allow s erasability and reprogramrnability. The Altera EP910 Erasable Program m able Logic Device may be used to implement over 900 equiva
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24-MACROCELL
20//A
tAC01
EP910
EP910-35
FLIPFLOP SCHEMATIC
10KHZ
74HC
EP910-30
EP910-40
EP910A
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PDF
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EP910
Abstract: altera EP910
Text: EP910 EPLD Features • ■ ■ ■ ■ ■ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD as low as 12 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 100 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs
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EP910
24-macrocell
EP910,
EP910T,
EP910I
44-pin
40-pin
24-bit
altera EP910
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PDF
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Untitled
Abstract: No abstract text available
Text: Features a General Description Altera's EP910T Erasable Programmable Logic Device EPLD is a lowcost, high-performance version of the EP910 device. This EPLD operates in a turbo mode that is optimized for high-speed applications. The Turbo Bit in the device is preset at the factory. The EP910T EPLD is available in OTP
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EP910T
EP910
40-pin,
600-mil
44-pin
EP910TEPLD
EP910-30T
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PDF
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EP9122
Abstract: smd 57b EP9100 EP9101 EP9102 EP9108 EP9109 EP9110 EP9115 EP9116
Text: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines Delays are ±5% or +2 nSt Tap Total 5, 10, 15, 20 6, 12, 18, 24 7, 14, 21, 28 8, 16, 24, 32 9, 18, 27, 36 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45, 60 J-Lead P/N 25 30 35 40 45 50 60 75 t Whichever is greater.
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EP9100
EP9115
EP9108
EP9123
EP9101
EP9116
EP9109
EP9124
EP9102
EP9117
EP9122
smd 57b
EP9110
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PDF
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programming manual EPLD EPS448
Abstract: Altera EPM5128 EPM7064-12 leap u1 EP-900910 PLE3-12a tcl tv circuit altera eplds EP610 "pin compatible" ALTERA MAX 5000
Text: Data Book TENTH ANNIVERSARY A Decade of Leadership A u g u s t 1993 Data Book August 1993 A-DB-0793-01 Altera, MAX, and M A X+PLUS are registered trademarks of Altera Corporation. The following, among others, are trademarks of Altera Corporation: AHDL, M AX+PLUS II, PL-ASAP2, PLDS-HPS, PLS-ADV, PLS-ES, PLS-FLEX8, PLS-FLEX8/H P, PLS-FLEX8/SN , PLS-HPS, PLS-STD, PLS-W S/H P,
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-DB-0793-01
EP330,
EP610,
EP610A,
EP610T,
EP910,
EP910A,
EP910T,
EP1810,
EP1810T,
programming manual EPLD EPS448
Altera EPM5128
EPM7064-12
leap u1
EP-900910
PLE3-12a
tcl tv circuit
altera eplds
EP610 "pin compatible"
ALTERA MAX 5000
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PDF
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EP910PC-30
Abstract: EP910PC-40 EP910PC35 EP910PC-35 EP9100c EP910LC-30 EP910J EP910JC30 EP910LC-40 EP910JC-30
Text: EP910 HIGH-PERFORMANCE 24-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3187. OCTOBER 1988-REVISED AUQUST 1989 DUAL-IN-LINE PAC KA G E • High-Density (Over 900 Gates) Replacement for TTL and 74HC H O P VIEW) clk C 1 V_J40 39 iC 2 • Virtually Zero Standby Power. Typ 20 nA
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EP910
24-MACROCELL
D3187.
1988-REVISED
44-PIN
EP910PC-30
EP910PC-40
EP910PC35
EP910PC-35
EP9100c
EP910LC-30
EP910J
EP910JC30
EP910LC-40
EP910JC-30
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PDF
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altera EP910
Abstract: EP910-T IEP910 altera eplds EP910EPLD
Text: t ALTERA 47E CORP D • 05*15372 00020TM - r Tfl? o - ■ c f ALT EP910 EPLDs High-Performance 24-Macrocell Devices Data Sheet September 1991, ver. 2 □ □ Features □ □ □ □ □ □ □ General Description Altera's EP910 Erasable Programmable Logic Devices EPLDs can
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00020TM
EP910
24-Macrocell
EP910T
EP910-30T
altera EP910
EP910-T
IEP910
altera eplds
EP910EPLD
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PDF
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TD 265 N 600 KOC
Abstract: core i5 520 Scans-049 camtex trays sii Product Catalog EPM9560 film hot BT 342 project TIL Display 7160S
Text: 1996 Data Book Data Book June 1996 A-DB-0696-01 Altera, MAX, M A X+PLUS, FLEX, FLEX 10K, FLEX 8000, FLEX 8000A, MAX 9000, MAX 7000, MAX 7000E, MAX 7000S, FLASHlogic, MAX 5000, Classic, M AX+PLUS II, PL-ASAP2, PLDshell Plus, FastTrack, AHDL, MPLD, Turbo Bit, BitBlaster, PENGN, RIPP 10, PLS-ES, ClockLock, ClockBoost,
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-DB-0696-01
7000E,
7000S,
EPF10K100,
EPF10K70,
EPF10K50,
EPF10K40,
EPF10K30,
EPF10K20,
EPF10K10,
TD 265 N 600 KOC
core i5 520
Scans-049
camtex trays
sii Product Catalog
EPM9560
film hot
BT 342 project
TIL Display
7160S
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PDF
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EP610
Abstract: ep910 programmer TI EP610 EP610-25 EP1810 EP910 ALTERA MAX 5000 programming EP6101-10
Text: Classic EPLD Family January 1998. ver. 4 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family w ith logic densities of 300 to 900 usable gates see Fable 1 Device erasure and reprogram m ing w ith advanced, non-volatile EPROM configuration elements
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OCR Scan
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EP1810
68-pin
EP610
ep910 programmer
TI EP610
EP610-25
EP910
ALTERA MAX 5000 programming
EP6101-10
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PDF
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Untitled
Abstract: No abstract text available
Text: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines - - 5, 10, 15,20 6, 12, 18, 24 7, 14, 21,28 8,16, 24, 32 9, 18, 27, 36 10, 20, 30, 40 12, 24,36, 48 15, 30,45, 60 Gull-Wing P/N J-Lead P/N Delays are ±5% or ±2 nS
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OCR Scan
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EP9100
EP9101
EP9102
EP9103
EP9104
EP9105
EP9106
EP9107
EP9115
EP9116
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PDF
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910T
Abstract: No abstract text available
Text: EP910T EPLD Features □ □ □ □ General Description A lte ra 's E P 910T E rasable P ro g ra m m a b le L ogic D ev ice E P L D is a low cost, h ig h -p erfo rm a n ce version o f the E P 910 d ev ice. T h is E PL D o p erates in a tu rbo m o d e that is op tim ized for h ig h -sp eed ap p licatio n s. T h e T u rb o Bit
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EP910T
EP910TEPLD
EP910-30T
910T
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PDF
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pin configuration of ic 7483
Abstract: pin diagram for IC 7483 altera ep910i EP610I
Text: / 7 \| H i-fczi d / 7 \ /A j U I □ rv À \ Application Brief 100 March 1995, ver. 3 Introduction Understanding Classic, MAX 5000 & MAX 7000 Timing Altera devices provide device perform ance that is consistent from sim ulation to application. Before program m ing a device, you can
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