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    DM74S11 Price and Stock

    Rochester Electronics LLC DM74S11N

    IC GATE AND 3CH 3-INP 14DIP
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    DigiKey DM74S11N Tube 1,158
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    onsemi DM74S11N

    IC GATE AND 3CH 3-INP 14MDIP
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    DigiKey DM74S11N Tube 25
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    onsemi DM74S113N

    IC FF JK TYPE DUAL 14DIP
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    DigiKey DM74S113N Bag 25
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    onsemi DM74S112N

    IC FF JK TYPE DUAL 1BIT 16DIP
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    DigiKey DM74S112N Bag 25
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    National Semiconductor Corporation DM74S113N

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    Bristol Electronics DM74S113N 299
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    DM74S113N 23
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    Quest Components DM74S113N 441
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    DM74S113N 239
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    DM74S113N 91
    • 1 $3.2
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    DM74S113N 2
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    DM74S11 Datasheets (27)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    DM74S11 National Semiconductor Triple 3-Input AND Gate Original PDF
    DM74S112 National Semiconductor Dual Negative-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs Original PDF
    DM74S112CW Fairchild Semiconductor Dual Negative-Edge-Triggered J-K Flip-Flop with Preset Clear and Complementary Outputs Original PDF
    DM74S112M Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    DM74S112N Fairchild Semiconductor Dual Negative-Edge-Triggered J-K Flip-Flop with Preset Clear and Complementary Outputs Original PDF
    DM74S112N National Semiconductor Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs Original PDF
    DM74S112N Fairchild Semiconductor Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs Scan PDF
    DM74S112N Unknown TTL Data Book 1980 Scan PDF
    DM74S112N Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    DM74S112N National Semiconductor Misc. Data Book Scans 1975/76 Scan PDF
    DM74S112N National Semiconductor Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs Scan PDF
    DM74S113 National Semiconductor Dual Negative-Edge-Triggered J-K Flip-Flop with Preset and Complementary Ouputs Original PDF
    DM74S113N Unknown TTL Data Book 1980 Scan PDF
    DM74S113N Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    DM74S113N National Semiconductor Misc. Data Book Scans 1975/76 Scan PDF
    DM74S114D Unknown IC Datasheet (Short Description and Cross Reference Only) Scan PDF
    DM74S114N Unknown TTL Data Book 1980 Scan PDF
    DM74S114N National Semiconductor Misc. Data Book Scans 1975/76 Scan PDF
    DM74S114N National Semiconductor Dual Negative Edge Triggered Master-Slave J-K Flip-Flops with Preset, Common Clear, Common Clock and Complementary Outputs Scan PDF
    DM74S11N Fairchild Semiconductor Triple 3-Input AND Gate Original PDF

    DM74S11 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    DM74S112

    Abstract: DM54S112 DM54S112J DM74S112N J16A N16E
    Text: DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs sition time of the negative going edge of the clock pulse. Data on the J and K inputs can be changed while the clock is high or low without affecting the outputs as long as setup


    Original     		DM74S112 DM74S112 DM54S112 DM54S112J DM74S112N J16A N16E PDF

    C1995

    Abstract: DM54S112 DM54S112J DM74S112 DM74S112N J16A N16E
    Text: DM54S112 DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of


    Original     		DM54S112 DM74S112 C1995 DM54S112J DM74S112N J16A N16E PDF

    DM74S11

    Abstract: DM54S11J DM54S11W DM74S11N J14A N14A W14B
    Text: DM74S11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which performs the logic AND function. Connection Diagram Dual-In-Line Package DS006447-1 Order Number DM54S11J, DM54S11W or DM74S11N See Package Number J14A, N14A or W14B


    Original     		DM74S11 DS006447-1 DM54S11J, DM54S11W DM74S11N DS006447 DM74S11 DM54S11J DM74S11N J14A N14A W14B PDF

    74S112

    Abstract: 54 dual JK fairchild
    Text: Revised April 2000 DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and


    Original     		DM74S112 29-JUL-00) ////roarer/root/data13/imaging/BIT. 04/08032000/FAIR/08022000/DM74S112 DM74S112N DM74S112N DM74S112CW 74S112 54 dual JK fairchild PDF

    DM74S11

    Abstract: DM74S11N MS-001 N14A
    Text: Revised April 2000 DM74S11 Triple 3-Input AND Gate General Description This device contains three independent gates each of which performs the logic AND function. Ordering Code: Order Number DM74S11N Package Number N14A Package Description 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, 0.300 Wide


    Original     		DM74S11 DM74S11N 14-Lead MS-001, DS006447 DM74S11 DM74S11N MS-001 N14A PDF

    DM74S113N

    Abstract: C1995 DM54S113 DM54S113J DM74S113 J14A N14A
    Text: DM54S113 DM74S113 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of


    Original     		DM54S113 DM74S113 DM74S113N C1995 DM54S113J J14A N14A PDF

    DM74S112

    Abstract: MS-001 N16E
    Text: Revised April 2000 DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and


    Original     		DM74S112 DM74S112 MS-001 N16E PDF

    DM74S112

    Abstract: MS-001 N16E
    Text: Revised April 2000 DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and


    Original     		DM74S112 DM74S112 MS-001 N16E PDF

    74s112n

    Abstract: 54S112 74S112
    Text: I R C H I L D S E M I C O N D U C T O R TM DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description sition tim e of th e negative going edge o f the clock pulse. Data on the J and K inputs can be changed w hile the clock


    OCR Scan     		DM74S112 74s112n 54S112 74S112 PDF

    preset 100 K

    Abstract: DM54S112 DM54S112J DM74S112 DM74S112N J16A N16E
    Text: , June 1989 DM54S112/DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig­ gered J-K flip-flops with complementary outputs. The J and


    OCR Scan     		DM54S112/DM74S112 preset 100 K DM54S112 DM54S112J DM74S112 DM74S112N J16A N16E PDF

    DM54

    Abstract: DM74 DM74S114
    Text: ÆjA Semiconductor DM54S114/DM74S114 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Common Clear, Common Clock and Complementary Outputs General Description Absolute Maximum Ratings Note d T h is d e v ic e c o n ta in s tw o n e g a tiv e -e d g e -trig g e re d J-K


    OCR Scan     		DM54S114/DM74S114 DM54 DM74 DM74S114 PDF

    Untitled

    Abstract: No abstract text available
    Text: S E M IC O N D U C T O R tm DM74S11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which perform s the logic AN D function. Connection Diagram 3 Ai Y3 1 Y1 c3 B Vet. C 13 12 1 1 1 9 8 D jal-ln-Lin e Packa ge


    OCR Scan     		DM74S11 DM54S11J, DM54S11W DM74S11N DS006447 PDF

    Untitled

    Abstract: No abstract text available
    Text: S E M IC O N D U C T O R tm DM74S11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which performs the logic AND function. Connection Diagram D jal-ln-Lin e Packa 3 Va. Y1 C lM Ai B3 c3 11 12 13 Y3 9 1 1


    OCR Scan     		DM74S11 DM54S11J, DM54S11W DM74S11N DS006447 PDF

    DM54S11

    Abstract: DM54S11W DM74S11N J14A N14A W14B
    Text: , June 1989 DM54S11/DM74S11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which performs the logic AND function. Connection Diagram Dual-In-Line Package V, , U1 VI C3 B3 A3 Y3 Order Number DM54S11J, DM54S11W or DM74S11N


    OCR Scan     		DM54S11/DM74S11 TL/F/6447-1 DM54S11 DM54S11W DM74S11N TL/F/6447 RRD-B30M105/Printed J14A N14A W14B PDF

    Untitled

    Abstract: No abstract text available
    Text: Ju n e 1989 Semiconductor DM54S113/DM74S113 Dual N egative-Edge-Triggered M aster-Slave J-K Flip-Flops with Preset and C om plem en tary O utputs General Description T h is d evice co ntain s tw o in d epen d ent negative-edge-trig­ gered J - K flip-flops with co m p lem entary outputs. T h e J and


    OCR Scan     		DM54S113/DM74S11 DM54S113/DM74S113 PDF

    DM54

    Abstract: DM54S11 DM54S11W DM74S11 DM74S11N J14A N14A W14B
    Text: National Semiconductor DM54S11/DM74S11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which performs the logic AND function. Connection Diagram □ual-ln-Line Package T L /F /6 4 4 7 -1 Order Number DM54S11J, DM54S11W or DM74S11N


    OCR Scan     		DM54S11/DM74S11 DM54S11 DM54S11W DM74S11N DM54 DM74S11 J14A N14A W14B PDF

    74S112N

    Abstract: No abstract text available
    Text: R C H U - P S E M IC O N D U C T O R tm DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description sition tim e of th e negative going edge o f the clock pulse. Data on the J and K inputs can be changed w hile the clock


    OCR Scan     		DM74S112 16-Lead 54S112J Q-325 74S112N PDF

    Untitled

    Abstract: No abstract text available
    Text: June 1989 DM54S112/DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig­ gered J-K flip-flops with complementary outputs. The J and


    OCR Scan     		DM54S112/DM74S112 PDF

    Untitled

    Abstract: No abstract text available
    Text: June 1989 DM54S11/DM74S11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which performs the logic AND function. Connection Diagram Dual-In-Line Package V,:r U1 VI C3 B3 A3 Y3 Order Number DM54S11J, DM54S11W or DM74S11N


    OCR Scan     		DM54S11/DM74S11 DM54S11J, DM54S11W DM74S11N N14AorW14B 105/Printed PDF

    DM74S112N

    Abstract: DM54S112 DM54S112J DM74S112 J16A N16E
    Text: DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs sition tim e o f th e negative going edge o f the clock pulse. Data on the J and K inputs can be changed w hile the clock is high o r low w ithout affecting the outputs as long as setup


    OCR Scan     		DM74S112 16-Lead DM74S112N DM54S112 DM54S112J DM74S112 J16A N16E PDF

    Untitled

    Abstract: No abstract text available
    Text: S112 National Semiconductor DM54S112/DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig­ gered J-K flip-flops with complementary outputs. The J and


    OCR Scan     		DM54S112/DM74S112 PDF

    DM54S113

    Abstract: DM54S113J DM74S113 DM74S113N J14A N14A
    Text: DM54S113/DM74S113 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset and Complementary Outputs General Description This device contains two independent negative-edge-trig­ gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of


    OCR Scan     		DM54S113/DM74S113 280J1 DM54S113 DM54S113J DM74S113 DM74S113N J14A N14A PDF

    J14A

    Abstract: N14A W14B DM54S11J DM54S11W DM74S11 DM74S11N
    Text: S E M IC O N D U C T O R tm DM74S11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which perform s the logic A N D function. Connection Diagram Dual-ln-Line Package DS006447-1 Order Number DM54S11J, DM54S11W or DM74S11N


    OCR Scan     		DM74S11 DS006447-1 DM54S11J, DM54S11W DM74S11N DS006447 J14A N14A W14B DM54S11J DM74S11 PDF

    Untitled

    Abstract: No abstract text available
    Text: S112 National Semiconductor DM54S112/DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and


    OCR Scan     		DM54S112/DM74S112 PDF