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    Untitled

    Abstract: No abstract text available
    Text: CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 18 Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1310JV18 – 2M x 8 CY7C1910JV18 – 2M x 9


    Original     		PDF CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 CY7C1310JV18 CY7C1312JV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 18-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1310JV18 – 2M x 8 CY7C1910JV18 – 2M x 9


    Original     		PDF 18-Mbit CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 CY7C1310JV18 CY7C1910JV18 CY7C1312JV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 18 Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■


    Original     		PDF CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 CY7C1310JV18 CY7C1312JV18

    Untitled

    Abstract: No abstract text available
    Text: THIS SPEC IS OBSOLETE Spec No: 001-43127 Spec Title: CY7C1310JV18/CY7C1910JV18/CY7C1312JV18/ CY7C1314JV18, 18-MBIT QDR R -II SRAM 2WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar (NJY) Replaced by: NONE CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18


    Original     		PDF CY7C1310JV18/CY7C1910JV18/CY7C1312JV18/ CY7C1314JV18, 18-MBIT CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 CY7C1310JV18