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    CY7C1314JV18 Price and Stock

    Rochester Electronics LLC CY7C1314JV18-250BZXC

    IC SRAM 18MBIT PAR 165FBGA
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    DigiKey CY7C1314JV18-250BZXC Tray 9
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    • 10 $34.96
    • 100 $34.96
    • 1000 $34.96
    • 10000 $34.96
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    Infineon Technologies AG CY7C1314JV18-250BZXC

    IC SRAM 18MBIT PAR 165FBGA
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    DigiKey CY7C1314JV18-250BZXC Tray
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    Cypress Semiconductor CY7C1314JV18-250BZXC

    QDR SRAM, 512KX36, 0.45ns PBGA165 '
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    Rochester Electronics CY7C1314JV18-250BZXC 289 1
    • 1 $33.62
    • 10 $33.62
    • 100 $31.6
    • 1000 $28.58
    • 10000 $28.58
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    CY7C1314JV18 Datasheets (1)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1314JV18-250BZXC Cypress Semiconductor 18 Mbit QDR -II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V Original PDF

    CY7C1314JV18 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 18 Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1310JV18 – 2M x 8 CY7C1910JV18 – 2M x 9


    Original     		CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 CY7C1310JV18 CY7C1312JV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 18-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1310JV18 – 2M x 8 CY7C1910JV18 – 2M x 9


    Original     		18-Mbit CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 CY7C1310JV18 CY7C1910JV18 CY7C1312JV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 18 Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■


    Original     		CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 CY7C1310JV18 CY7C1312JV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: THIS SPEC IS OBSOLETE Spec No: 001-43127 Spec Title: CY7C1310JV18/CY7C1910JV18/CY7C1312JV18/ CY7C1314JV18, 18-MBIT QDR R -II SRAM 2WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar (NJY) Replaced by: NONE CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18


    Original     		CY7C1310JV18/CY7C1910JV18/CY7C1312JV18/ CY7C1314JV18, 18-MBIT CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 CY7C1310JV18 PDF