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CY7C1313CV18 Price and Stock

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Infineon Technologies AG CY7C1313CV18-250BZC IC SRAM 18MBIT PAR 165FBGA
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DigiKey	CY7C1313CV18-250BZC	Tray			136	1 - 10 - 100 - 1000 $33.65397 10000 $33.65397	Buy Now
Rochester Electronics LLC CY7C1313CV18-250BZC IC SRAM 18MBIT PAR 165FBGA
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DigiKey	CY7C1313CV18-250BZC	Tray			9	1 - 10 $34.96 100 $34.96 1000 $34.96 10000 $34.96	Buy Now
Infineon Technologies AG CY7C1313CV18-250BZI IC SRAM 18MBIT PAR 165FBGA
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DigiKey	CY7C1313CV18-250BZI	Tray				1 - 10 - 100 - 1000 - 10000 -	Buy Now
Rochester Electronics LLC CY7C1313CV18-167BZC IC SRAM 18MBIT PAR 165FBGA
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DigiKey	CY7C1313CV18-167BZC	Tray			10	1 - 10 $31.96 100 $31.96 1000 $31.96 10000 $31.96	Buy Now
Infineon Technologies AG CY7C1313CV18-167BZC IC SRAM 18MBIT PAR 165FBGA
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DigiKey	CY7C1313CV18-167BZC	Tray			136	1 - 10 - 100 - 1000 $30.93772 10000 $30.93772	Buy Now

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CY7C1313CV18 Datasheets (6)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY7C1313CV18		Cypress Semiconductor	18-Mbit QDR-II SRAM 4-Word Burst Architecture		Original	PDF
CY7C1313CV18-167BZC		Cypress Semiconductor	18-Mbit QDR -II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 1.7 to 1.9 V		Original	PDF
CY7C1313CV18-200BZC		Cypress Semiconductor	18-Mbit QDR -II SRAM 4-Word Burst Architecture		Original	PDF
CY7C1313CV18-200BZXI		Cypress Semiconductor	18-Mbit QDR -II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 1.7 to 1.9 V		Original	PDF
CY7C1313CV18-250BZC		Cypress Semiconductor	18-Mbit QDR -II SRAM 4-Word Burst Architecture		Original	PDF
CY7C1313CV18-250BZI		Cypress Semiconductor	18-Mbit QDR -II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 1.7 to 1.9 V		Original	PDF

CY7C1313CV18 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
CY7C1311CV18 Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18 Text: CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■	Original	CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit CY7C1311CV18 CY7C1313CV18 CY7C1311CV18 CY7C1313CV18 CY7C1315CV18 CY7C1911CV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1311CV18 CY7C1911CV18 CY7C1313CV18 CY7C1315CV18 PRELIMINARY 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports • QDR-II operates with 1.5 cycle read latency when the DLL is enabled	Original	CY7C1311CV18 CY7C1911CV18 CY7C1313CV18 CY7C1315CV18 18-Mbit 300-MHz 600MHz)	PDF
Untitled Abstract: No abstract text available Text: THIS SPEC IS OBSOLETE Spec No: 001-07165 Spec Title: 7C1313CV18/CY7C1315CV18, 18-MBIT QDR R II SRAM 4-WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar (NJY) Replaced by: NONE CY7C1313CV18 CY7C1315CV18 18-Mbit QDR II SRAM 4-Word Burst Architecture 18-Mbit QDR® II SRAM 4-Word Burst Architecture	Original	7C1313CV18/CY7C1315CV18, 18-MBIT CY7C1313CV18 CY7C1315CV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1313CV18 CY7C1315CV18 18-Mbit QDR II SRAM 4-Word Burst Architecture 18-Mbit QDR® II SRAM 4-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1313CV18 – 1M x 18 •	Original	CY7C1313CV18 CY7C1315CV18 18-Mbit CY7C1313CV18	PDF
CY7C1311CV18 Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18 Text: CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■	Original	CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit CY7C1311CV18 CY7C1313CV18 CY7C1311CV18 CY7C1313CV18 CY7C1315CV18 CY7C1911CV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1313CV18 CY7C1315CV18 18-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1313CV18 – 1M x 18 ■ 300 MHz clock for high bandwidth ■ 4-word burst for reducing address bus frequency	Original	CY7C1313CV18 CY7C1315CV18 18-Mbit CY7C1313CV18	PDF