CY7C1163V18 Search Results

CY7C1163V18 Datasheets (2)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY7C1163V18		Cypress Semiconductor	18-Mbit QDR-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)		Original	PDF
CY7C1163V18-400BZC		Cypress Semiconductor	18-Mbit QDR -II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)		Original	PDF

CY7C1163V18 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
Untitled Abstract: No abstract text available Text: THIS SPEC IS OBSOLETE Spec No: 001-06582 Spec Title: CY7C1161V18/CY7C1176V18/CY7C1163V18/ CY7C1165V18, 18-MBIT QDR TM -II+ SRAM 4-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) Sunset Owner: Jayasree Nayar (njy) Replaced by: NONE CY7C1161V18, CY7C1176V18	Original	PDF	CY7C1161V18/CY7C1176V18/CY7C1163V18/ CY7C1165V18, 18-MBIT CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18
Untitled Abstract: No abstract text available Text: CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz to 400 MHz clock for high bandwidth	Original	PDF	CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit CY7C1161V18, CY7C1176V18, CY7C1163V18, CY7C1165V18
CY7C1161V18 Abstract: CY7C1163V18 CY7C1165V18 CY7C1176V18 Text: CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz to 400 MHz clock for high bandwidth	Original	PDF	CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit CY7C1161V18 CY7C1163V18 CY7C1165V18 CY7C1176V18
Untitled Abstract: No abstract text available Text: CY7C1176V18 CY7C1163V18 CY7C1165V18 PRELIMINARY 18-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300 MHz to 400 MHz clock for high bandwidth	Original	PDF	CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit CY7C1176V18/CY7C1163V18/CY7C1165V18 CY7C1176BV18
CY7C1161V18 Abstract: CY7C1163V18 CY7C1165V18 CY7C1176V18 Text: CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 18-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz to 400 MHz clock for high bandwidth	Original	PDF	CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 18-Mbit CY7C1161V18 CY7C1163V18 CY7C1165V18 CY7C1176V18
Untitled Abstract: No abstract text available Text: CY7C1163V18 CY7C1165V18 PRELIMINARY 18-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300 MHz to 400 MHz clock for high bandwidth	Original	PDF	CY7C1163V18 CY7C1165V18 18-Mbit
CY7C1163V18 Abstract: CY7C1263V18 EP3SL150F1152C2 Text: AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III and Stratix IV Devices July 2008, v1.1 Introduction QDRII+ and the QDRII SRAM devices are ideally suited for bandwidth– intensive and low-latency applications such as controller buffer memory, look-up tables LUTs ,	Original	PDF
CY7C1163V18 Abstract: EP3SL150F1152C2 qdrii sram digital clock project report Text: Design Guidelines for Implementing QDRII+ & QDRII SRAM Interfaces in Stratix III Devices Application Note 461 June 2007, v1.0 Introduction QDRII+ and QDRII SRAM devices are ideally suited for bandwidth– intensive, and low-latency applications such as controller buffer memory,	Original	PDF