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    Microchip Technology Inc AFS090-FG256

    IC FPGA 75 I/O 256FBGA
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    DigiKey AFS090-FG256 Tray 90
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    Microchip Technology Inc AFS090-2FG256

    IC FPGA 75 I/O 256FBGA
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    Microchip Technology Inc AFS090-FG256I

    IC FPGA 75 I/O 256FBGA
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    DigiKey AFS090-FG256I Tray 90
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    Microchip Technology Inc AFS090-FGG256

    IC FPGA 75 I/O 256FBGA
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    EBV Elektronik AFS090-FGG256 53 Weeks 90
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    Microchip Technology Inc AFS090-1FG256

    IC FPGA 75 I/O 256FBGA
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    DigiKey AFS090-1FG256 Tray 90
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    Find more AFS090 price and stock on Findchips.com

    AFS090 Datasheets (66)

    Part ECAD Model Manufacturer Description Curated Type PDF
    AFS090-1FG256 Actel FUSION Mixed Signal PSC's 90K System Gates Original PDF
    AFS090-1FG256 Microsemi Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 75 I/O 256FBGA Original PDF
    AFS090-1FG256I Actel FUSION Mixed Signal PSC's 90K System Gates Original PDF
    AFS090-1FG256I Microsemi Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 75 I/O 256FBGA Original PDF
    AFS090-1FGG256 Actel FUSION Mixed Signal PSC's 90K System Gates Original PDF
    AFS090-1FGG256 Microsemi Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 75 I/O 256FBGA Original PDF
    AFS090-1FGG256I Actel FUSION Mixed Signal PSC's 90K System Gates Original PDF
    AFS090-1FGG256I Microsemi Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 75 I/O 256FBGA Original PDF
    AFS090-1QN108 Actel FPGA Fusion Family 90K Gates 1282.05MHz Commercial 130nm (CMOS) Technology 1.5V 108-Pin QFN Original PDF
    AFS090-1QN108I Actel FPGA Fusion Family 90K Gates 1282.05MHz Industrial 130nm (CMOS) Technology 1.5V 108-Pin QFN Original PDF
    AFS090-1QN180 Actel FPGA Fusion Family 90K Gates 1282.05MHz Commercial 130nm (CMOS) Technology 1.5V 180-Pin QFN Original PDF
    AFS090-1QN180I Actel FPGA Fusion Family 90K Gates 1282.05MHz Industrial 130nm (CMOS) Technology 1.5V 180-Pin QFN Original PDF
    AFS090-1QNG108 Actel FUSION Mixed Signal PSC's 90K System Gates Original PDF
    AFS090-1QNG108 Microsemi Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 37 I/O 108QFN Original PDF
    AFS090-1QNG108I Actel FUSION Mixed Signal PSC's 90K System Gates Original PDF
    AFS090-1QNG108I Microsemi Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 37 I/O 108QFN Original PDF
    AFS090-1QNG180 Actel FUSION Mixed Signal PSC's 90K System Gates Original PDF
    AFS090-1QNG180 Microsemi Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 60 I/O 180QFN Original PDF
    AFS090-1QNG180I Actel FUSION Mixed Signal PSC's 90K System Gates Original PDF
    AFS090-1QNG180I Microsemi Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 60 I/O 180QFN Original PDF

    AFS090 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    design of 16-1 multiplexer

    Abstract: ACTEL FUSION AFS1500 QN108 QN180 FG484 FG484 input and output pin details FG256 FG676 PQ208 AFS600-FG256
    Text: 16 – Prototyping With AFS600 for Smaller Devices This document is designed as an aid for customers who may ultimately wish to use one of the smaller members of the Fusion family AFS090 and/or AFS250 . The first device available in the Fusion family is the AFS600, which can be used as a development or prototyping platform for the


    Original     		PDF AFS600 AFS090 AFS250) AFS600, AFS250 AFS600. AFS600-FG256 design of 16-1 multiplexer ACTEL FUSION AFS1500 QN108 QN180 FG484 FG484 input and output pin details FG256 FG676 PQ208

    AC270

    Abstract: verilog code for slave SPI with FPGA spi slave AFS090
    Text: Application Note AC270 SPI Flash Emulation for Fusion Devices Design Example Contents General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


    Original     		PDF AC270 AC270 verilog code for slave SPI with FPGA spi slave AFS090

    AC307

    Abstract: SPARTAN 3E STARTER BOARD L262144 memory 2114 XILINX/SPARTAN 3E STARTER BOARD AFS090 generic SPI AFS-EVAL
    Text: Application Note AC307 Configuring SRAM FPGAs Using Actel Fusion Introduction Due to the nature of SRAM technology, SRAM-based FPGAs are volatile and lose their configuration when powered off, so they must be reconfigured at every power-up. Hence, almost every system using SRAMbased FPGAs contains an additional nonvolatile memory, such as flash PROM or EEPROM, to store the


    Original     		PDF AC307 AC307 SPARTAN 3E STARTER BOARD L262144 memory 2114 XILINX/SPARTAN 3E STARTER BOARD AFS090 generic SPI AFS-EVAL

    ACTEL FUSION AFS1500

    Abstract: FlashPro3 PQ208 QN108 QN180 M1AFS1500 AFS250 rc oscillator M-LVDS
    Text: Preliminary v1.7 Actel Fusion Mixed-Signal FPGAs Family with Optional ARM® Support Features and Benefits – Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz Low Power Consumption High-Performance Reprogrammable Flash Technology • • • • • Single 3.3 V Power Supply with On-Chip 1.5 V Regulator


    Original     		PDF 130-nm, 128-Bit ACTEL FUSION AFS1500 FlashPro3 PQ208 QN108 QN180 M1AFS1500 AFS250 rc oscillator M-LVDS

    verilog code voltage regulator

    Abstract: verilog code for adc verilog code voltage regulator vhdl verilog code for amba apb bus 16bit microprocessor using vhdl simple ADC Verilog code verilog code for apb vhdl code for Clock divider for FPGA vhdl code for frequency divider APB VHDL code
    Text: P ro du c t Br ie f CoreAI Product Summary Synthesis and Simulation Support Intended Use • Analog Interface Control Using a Microprocessor/ Microcontroller and an Actel FusionTM Device • Voltage, Current, and Temperature Monitoring Using a Microprocessor/Microcontroller and an


    Original     		PDF 51700066PB-0/3 verilog code voltage regulator verilog code for adc verilog code voltage regulator vhdl verilog code for amba apb bus 16bit microprocessor using vhdl simple ADC Verilog code verilog code for apb vhdl code for Clock divider for FPGA vhdl code for frequency divider APB VHDL code

    AFS600-FG256

    Abstract: zo 103 ma 75 607 A54 ZENER flashpro3 schematic mark AT0 Unipolar PC atx 400 P4 power supply diagram zener Diode B23 PQ208 QN108 QN180
    Text: Preliminary v1.7 Actel Fusion Mixed-Signal FPGAs Family with Optional ARM® Support Features and Benefits – Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz Low Power Consumption High-Performance Reprogrammable Flash Technology • • • • • Single 3.3 V Power Supply with On-Chip 1.5 V Regulator


    Original     		PDF 130-nm, 128-Bit AFS600-FG256 zo 103 ma 75 607 A54 ZENER flashpro3 schematic mark AT0 Unipolar PC atx 400 P4 power supply diagram zener Diode B23 PQ208 QN108 QN180

    A54 ZENER

    Abstract: AFS600-FG256 mark AT0 QN108 CORE8051 bipolar ROM
    Text: v2.0 Actel Fusion Family of Mixed-Signal FPGAs Features and Benefits In-System Programming ISP and Security High-Performance Reprogrammable Flash Technology Advanced Digital I/O • • • • • Secure ISP with 128-Bit AES via JTAG • FlashLock® to Secure FPGA Contents


    Original     		PDF 128-Bit 130-nm, A54 ZENER AFS600-FG256 mark AT0 QN108 CORE8051 bipolar ROM

    a51 ZENER DIODE

    Abstract: transistor 2n2222 bipolar ROM EQUIVALENCES TRANSISTOR LIST ProASIC3 lvds yl 1060
    Text: Revision 3 Fusion Family of Mixed Signal FPGAs Features and Benefits In-System Programming ISP and Security • ISP with 128-Bit AES via JTAG • FlashLock Designed to Protect FPGA Contents High-Performance Reprogrammable Flash Technology • • • •


    Original     		PDF 130-nm, 128-Bit a51 ZENER DIODE transistor 2n2222 bipolar ROM EQUIVALENCES TRANSISTOR LIST ProASIC3 lvds yl 1060

    AIRbus

    Abstract: No abstract text available
    Text: AIRbus Interface December 2000 ver. 1.00 Functional Specification 9  Features       Fixed width 8-, 16-, or 32-bit data transfers (dependent on the width of the data bus) Read and write access Four-way handshaking Arbitrary transaction latency Single-synchronous operation for higher performance and lower gate


    Original     		PDF

    AC270

    Abstract: pll02 ACTEL FUSION AFS1500 verilog code for slave SPI with FPGA
    Text: Application Note AC270 SPI Flash Emulation for Fusion Devices Design Example Contents General Description . . Functional Description Interface Details . . . . Utilization Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


    Original     		PDF AC270 AC270 pll02 ACTEL FUSION AFS1500 verilog code for slave SPI with FPGA

    peak china qfn 9 x 9 tray drawing

    Abstract: semi catalog AGL1000-FG484
    Text: IGLOO Handbook IGLOO Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – IGLOO Datasheet IGLOO Low-Power Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I


    Original     		PDF

    AFS090

    Abstract: No abstract text available
    Text: Advanced v0.2 Fusion Family of Mixed-Signal Flash FPGAs Features and Benefits • High Performance Reprogrammable Flash Technology • • • • • • • Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process Nonvolatile, Retains Program When Powered-Off


    Original     		PDF 130-nm, 64-Bit 32-Bit 12-Bit AFS090

    connect usb in vcd player circuit diagram

    Abstract: DIODE MARKING 534
    Text: IGLOOe Handbook IGLOOe Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – IGLOOe Datasheet IGLOOe Low-Power Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I


    Original     		PDF

    equivalent ZO 607

    Abstract: JESD 201 class 1A crystal k 1058 mosfet
    Text: Advanced v0.8 Fusion Family of Mixed-Signal Flash FPGAs ® with Optional Soft ARM Support Features and Benefits Low Power Consumption High-Performance Reprogrammable Flash Technology • • • • • • Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process


    Original     		PDF 130-nm, 32-Bit 12-Bit equivalent ZO 607 JESD 201 class 1A crystal k 1058 mosfet

    Untitled

    Abstract: No abstract text available
    Text: IGLOO Handbook IGLOO Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i-i Section I – IGLOO™ Datasheet IGLOO™ Low-Power Flash FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1


    Original     		PDF

    M2GL005

    Abstract: A2F060
    Text: Power Matters. CO LUT4 C OVFL LO UB ADD_S FPGA and SoC Product +/- Catalog ] A[17:0 D EN RO IN YP EN _SR CLK RST EN X ] C[43:0 SL D SN[43 D ] B[17:0 17 SHIFT >> 17 ASC SEL_C SECURITY RELIABILITY LOW POWER :0] SN-1[43 I N T E G R AT I O N FPGAs SoC FPGAs


    Original     		PDF MS2-002-14 M2GL005 A2F060

    Untitled

    Abstract: No abstract text available
    Text: IGLOO nano Handbook IGLOO nano Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – IGLOO nano Datasheet IGLOO nano Low-Power Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I


    Original     		PDF

    Power Track servo v1.0

    Abstract: No abstract text available
    Text: IGLOO Handbook IGLOO Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – IGLOO™ Datasheet IGLOO™ Low-Power Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1


    Original     		PDF

    IO191

    Abstract: vhdl code for fifo and transmitter actel FG484 package mechanical drawing
    Text: ProASIC 3L Low-Power Handbook ProASIC3L Low-Power Flash Device Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – ProASICL Low-Power Datasheet


    Original     		PDF

    proasic3e

    Abstract: No abstract text available
    Text: Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Introduction This document outlines the following device information: Clock Conditioning Circuits CCC features, PLL core specifications, functional descriptions, software configuration information,


    Original     		PDF A3P015, AGL015, AGLP030, AGLP060, AGLP125. proasic3e

    Untitled

    Abstract: No abstract text available
    Text: Radiation-Tolerant ProASIC 3 Handbook Radiation-Tolerant ProASIC3 Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – Radiation-Tolerant ProASIC3 FPGAs Datasheet


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: P ro du c t Br ie f Fusion Family of Mixed-Signal Flash FPGAs ® with Optional Soft ARM Support High-Performance Reprogrammable Flash Technology Low Power Consumption • • • • • • Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process Nonvolatile, Retains Program when Powered Off


    Original     		PDF 130-nm, 32-Bit 12-Bit 51700029PB-11/6

    IR 907

    Abstract: No abstract text available
    Text: IGLOO Handbook IGLOO Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – IGLOO Datasheet IGLOO Low-Power Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: Revision 2 Extended Temperature Fusion Family of Mixed Signal FPGAs Features and Benefits • Extended Temperature Tested • Each Device Tested from –55°C to 100°C Junction Temperature High-Performance Reprogrammable Flash Technology • • • • Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process


    Original     		PDF 130-nm, 32-Bit 12-Bit