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    8KX2 ROM Search Results

    8KX2 ROM Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    AM27S25DM Rochester Electronics LLC OTP ROM Visit Rochester Electronics LLC Buy
    AM27C256-55PC Rochester Electronics LLC OTP ROM, Visit Rochester Electronics LLC Buy
    27S185ALM/B Rochester Electronics LLC 27S185A - OTP ROM, 2KX4 Visit Rochester Electronics LLC Buy
    AM27C256-70PI Rochester Electronics LLC OTP ROM, 32KX8, 70ns, CMOS, PDIP28, DIP-28 Visit Rochester Electronics LLC Buy
    AM27C512-70JI Rochester Electronics LLC OTP ROM, 64KX8, 70ns, CMOS, PQCC32, LCC-32 Visit Rochester Electronics LLC Buy

    8KX2 ROM Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    256x16* STATIC RAM

    Abstract: 32Kx1 false RAMB16 XC2S100 XC2S15 XC2S150 XC2S200 XC2S30 XC2S50
    Text: Single-Port Block Memory Core v6.2 DS234 April 28, 2005 Features • Fully synchronous drop-in module for Virtex , Virtex-II, Virtex-II Pro, Virtex-4, Spartan™-II, Spartan-IIE, Spartan-3, and Spartan-3E FPGAs • Supports all three Virtex-II write mode options:


    Original     		PDF DS234 256x16* STATIC RAM 32Kx1 false RAMB16 XC2S100 XC2S15 XC2S150 XC2S200 XC2S30 XC2S50

    verilog code for dual port ram with axi interface

    Abstract: XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0
    Text: LogiCORE IP Block Memory Generator v7.1 DS512 April 24, 2012 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Block Memory Generator BMG core is an advanced memory constructor that generates area and performance-optimized memories


    Original     		PDF DS512 verilog code for dual port ram with axi interface XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0

    RAMB16

    Abstract: 16Kx1 XC2S100 XC2S15 XC2S150 XC2S200 XC2S30 XC2S50 XCV50 DS235
    Text: Dual-Port Block Memory Core v6.3 DS235 August 31, 2005 Features Product Specification Figure Top x-ref 1 • Drop-in module for Virtex , Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Spartan™-II, Spartan-IIE, Spartan-3, and Spartan-3E FPGAs ADDRA[n:0]


    Original     		PDF DS235 RAMB16 16Kx1 XC2S100 XC2S15 XC2S150 XC2S200 XC2S30 XC2S50 XCV50

    4kx4 rom

    Abstract: AZ 280 memory
    Text: Dual-Port Block Memory v6.1 DS235 May 21, 2004 Features Product Specification Figure Top x-ref 1 • Drop-in module for Virtex , Virtex-E, Virtex-II™, Virtex-II Pro™, Virtex-4™, Spartan-II™, Spartan-IIE, and Spartan-3™ FPGAs • Supports all three Virtex-II write mode options:


    Original     		PDF DS235 4kx4 rom AZ 280 memory

    RAMB16BWER

    Abstract: vhdl code hamming ecc 8kx1 RAM XC6VLX365T-FF1759-1 Xilinx Virtex6 Design Kit vhdl code hamming DS512 RAMB36 verilog code hamming vhdl spartan 3a
    Text: Block Memory Generator v3.2 DS512 June 24, 2009 Product Specification Introduction • The Xilinx LogiCORE IP Block Memory Generator core is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs.


    Original     		PDF DS512 RAMB16BWER vhdl code hamming ecc 8kx1 RAM XC6VLX365T-FF1759-1 Xilinx Virtex6 Design Kit vhdl code hamming RAMB36 verilog code hamming vhdl spartan 3a

    virtex-7

    Abstract: verilog code for dual port ram with axi interface AXI4 lite verilog virtex7 XC6SLX25T-2CSG324 DS512 XC6SLX RAMB18SDP 16Kx1 spartan6 block ram
    Text: LogiCORE IP Block Memory Generator v6.1 DS512 March 1, 2011 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Block Memory Generator BMG core is an advanced memory constructor that generates area and performance-optimized memories


    Original     		PDF DS512 virtex-7 verilog code for dual port ram with axi interface AXI4 lite verilog virtex7 XC6SLX25T-2CSG324 XC6SLX RAMB18SDP 16Kx1 spartan6 block ram

    XC5VLX50-FF676

    Abstract: ramb16bwer SPARTAN 3an spartan 3a vhdl code for 9 bit parity generator DS512 4VLX60 EE core SPARTAN 3an power of 2 vhdl code for 8 bit parity generator
    Text: Block Memory Generator v2.6 DS512 October 10, 2007 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Block Memory Generator core is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs.


    Original     		PDF DS512 XC5VLX50-FF676 ramb16bwer SPARTAN 3an spartan 3a vhdl code for 9 bit parity generator 4VLX60 EE core SPARTAN 3an power of 2 vhdl code for 8 bit parity generator

    XC6SL

    Abstract: SPARTAN 6 Configuration SPARTAN-6 DS512 RAMB36 RAMB18 RAMB18SDP hamming decoder vhdl code spartan 3 multiprocessor 2Kx18
    Text: Block Memory Generator v3.3 DS512 September 16, 2009 Product Specification Introduction • The Xilinx LogiCORE IP Block Memory Generator core is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs.


    Original     		PDF DS512 XC6SL SPARTAN 6 Configuration SPARTAN-6 RAMB36 RAMB18 RAMB18SDP hamming decoder vhdl code spartan 3 multiprocessor 2Kx18

    256x16* STATIC RAM

    Abstract: AZ 280 memory 4Kx4 rom DS234
    Text: Single-Port Block Memory v5.0 DS234 v0.1 November 1, 2002 Product Specification Features • Fully synchronous drop-in module for Virtex , Virtex-II, Virtex-II Pro™, Spartan™-II, Spartan-IIE, and Spartan-3 FPGAs • Supports all three Virtex-II write mode options:


    Original     		PDF DS234 xcv800 xcv1000 xcv50E xcv100E xcv200E xcv300R xcv400E xcv600E xcv1000E 256x16* STATIC RAM AZ 280 memory 4Kx4 rom DS234

    XAPP463

    Abstract: written RAMB16 vhdl code for bcd to seven segment display XC3S500E Seven Segment LED Display XC3S200 vhdl code for 4 bit even parity generator INIT01 Application Circuit xc3s200 XC3S2000
    Text: Application Note: Spartan-3 FPGA Family Using Block RAM in Spartan-3 Generation FPGAs R XAPP463 v2.0 March 1, 2005 Summary For applications requiring large, on-chip memories, Spartan -3 Generation FPGAs provides plentiful, efficient SelectRAM™ memory blocks. Using various configuration options,


    Original     		PDF XAPP463 256x72 XC3S1000L, XC3S1500L, XC3S4000L) XC3S100E, XC3S250E, XC3S500E, XC3S1200E, XC3S1600E) XAPP463 written RAMB16 vhdl code for bcd to seven segment display XC3S500E Seven Segment LED Display XC3S200 vhdl code for 4 bit even parity generator INIT01 Application Circuit xc3s200 XC3S2000

    Untitled

    Abstract: No abstract text available
    Text: Dual-Port Block Memory v5.0 DS235 v0.1 November 1, 2002 Product Specification Features • Drop-in module for Virtex , Virtex-E, Virtex-II, Virtex-II Pro™, Spartan™-II, Spartan-IIE, and Spartan-3 FPGAs • Supports all three Virtex-II write mode options:


    Original     		PDF DS235 xcv50E xcv100E xcv200E xcv300R xcv400E xcv600E xcv1000E xcv1600E xcv2000E

    100GBASE-R

    Abstract: QSFP 40G transceiver 40GBASE-R CPRI multi rate gearbox pcie gen3 QSFP optical active cable QSFP M20K 5SGX
    Text: Stratix V Device Family Overview SV51001-1.3 This document provides an overview of the Stratix V device features. Many of these features are enabled in the Quartus ® II software version 10.0. The remaining features will be enabled in future versions of the Quartus II software.


    Original     		PDF SV51001-1 28-nm 100GBASE-R QSFP 40G transceiver 40GBASE-R CPRI multi rate gearbox pcie gen3 QSFP optical active cable QSFP M20K 5SGX

    Untitled

    Abstract: No abstract text available
    Text: Stratix V Device Overview 2013.05.06 SV51001 Subscribe Feedback Many of the Stratix V devices and features are enabled in the Quartus® II software version 13.0. The remaining devices and features will be enabled in future versions of the Quartus II software.


    Original     		PDF SV51001 28-nm 40G/100G

    SV51001-3

    Abstract: interlaken 100GBASE-R 5SGXBB HF35-F1152
    Text: Stratix V Device Overview June 2012 SV51001-3.0 SV51001-3.0 This document provides an overview of the Stratix V devices and their features. Many of these devices and features are enabled in the Quartus® II software version 12.0. The remaining devices and features will be enabled in future versions of


    Original     		PDF SV51001-3 28-nm interlaken 100GBASE-R 5SGXBB HF35-F1152

    HF35-F1152

    Abstract: KF40-F1517 5sgxa3 eye-q 400 NF40-F1517 interlaken gf35 NF45 KF35-F1152
    Text: Stratix V Device Family Overview January 2011 SV51001-1.6 SV51001-1.6 This document provides an overview of the Stratix V devices and their features. Many of these devices and features are enabled in the Quartus ® II software version 10.1. The remaining devices and features will be enabled in future versions of the


    Original     		PDF SV51001-1 28-nm HF35-F1152 KF40-F1517 5sgxa3 eye-q 400 NF40-F1517 interlaken gf35 NF45 KF35-F1152

    Untitled

    Abstract: No abstract text available
    Text: Stratix V Device Handbook Volume 1: Overview and Datasheet 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V3-1.6 11.1 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos


    Original     		PDF

    RF40-F1517

    Abstract: KF40-F1517
    Text: Stratix V Device Handbook Volume 1: Overview and Datasheet Stratix V Device Handbook Volume 1: Overview and Datasheet 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V3-1.3 11.0 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.


    Original     		PDF

    pcie gen3

    Abstract: 28gbps
    Text: Stratix V Device Handbook Volume 1: Overview and Datasheet Stratix V Device Handbook Volume 1: Overview and Datasheet 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V3-1.2 11.0 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.


    Original     		PDF

    RF40-F1517

    Abstract: SV53001-2 HF35-F1152 5SGX
    Text: Stratix V Device Handbook Volume 1: Overview and Datasheet 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V3-1.7 11.1 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos


    Original     		PDF

    SV53001-2

    Abstract: KF35-F1152 QSFP 40G transceiver RF40-F1517 KF40-F1517 10G SFP HF35-F1152 H40-H1517 5SGXB9
    Text: Stratix V Device Handbook Volume 1: Overview and Datasheet 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V3-1.8 11.1 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos


    Original     		PDF

    UG331

    Abstract: CWda04 XAPP256 manual SPARTAN-3 XC3S400 evaluation kit vhdl code for rs232 receiver hcl l21 usb power supply circuit diagram hcl p38 CIRCUIT diagram R80515 XC3SD1800A-FG676 vhdl ethernet spartan 3a
    Text: Spartan-3 Generation FPGA User Guide Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families UG331 v1.6 December 3, 2009 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development


    Original     		PDF UG331 guides/ug332 UG331 CWda04 XAPP256 manual SPARTAN-3 XC3S400 evaluation kit vhdl code for rs232 receiver hcl l21 usb power supply circuit diagram hcl p38 CIRCUIT diagram R80515 XC3SD1800A-FG676 vhdl ethernet spartan 3a

    manual SPARTAN-3 XC3S400 evaluation kit

    Abstract: hcl l21 usb power supply circuit diagram verilog code for Modified Booth algorithm vhdl code for lcd of spartan3E UG331 TT 2222 Horizontal Output Transistor pins out dia verilog for 8 point fft using FPGA spartan3 vhdl code for ldpc decoder types of multipliers ge fanuc cpu 331
    Text: Spartan-3 Generation FPGA User Guide Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families UG331 v1.7 August 19, 2010 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development


    Original     		PDF UG331 guides/ug332 manual SPARTAN-3 XC3S400 evaluation kit hcl l21 usb power supply circuit diagram verilog code for Modified Booth algorithm vhdl code for lcd of spartan3E UG331 TT 2222 Horizontal Output Transistor pins out dia verilog for 8 point fft using FPGA spartan3 vhdl code for ldpc decoder types of multipliers ge fanuc cpu 331

    vhdl code for lcd of spartan3E

    Abstract: verilog code for Modified Booth algorithm vhdl code for rs232 receiver ge fanuc cpu 331 ug331 vhdl ethernet spartan 3a spartan 3e vga ucf barco 16 BIT ALU design with verilog/vhdl code TUTORIALS xilinx FFT
    Text: Spartan-3 Generation FPGA User Guide Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families UG331 v1.5 January 21, 2009 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development


    Original     		PDF UG331 guides/ug332 vhdl code for lcd of spartan3E verilog code for Modified Booth algorithm vhdl code for rs232 receiver ge fanuc cpu 331 ug331 vhdl ethernet spartan 3a spartan 3e vga ucf barco 16 BIT ALU design with verilog/vhdl code TUTORIALS xilinx FFT

    MULT18X18SIO

    Abstract: No abstract text available
    Text: 096 Spartan-3E FPGA Family: Functional Description R DS312-2 v1.1 March 21, 2005 Advance Product Specification Introduction As described in Architectural Overview, the Spartan -3E FPGA architecture consists of five fundamental functional elements: •


    Original     		PDF DS312-2 DS312-1, DS312-2, DS312-3, DS312-4, MULT18X18SIO