85C330 Search Results

85C330 Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
85C330		Silicon Integrated System	Data Buffer		Scan	PDF

85C330 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: SIS 85C330 _ Data Buffer Rev 1.1 Preliminary FEATURES • Provides 32 Bits D ata Buffer betw een C P U and 386 A T System • Provides 128 Bytes Internal C ache M em ory	OCR Scan	85C330 100-Pin 85C330	PDF
80387 Abstract: weitek 85C320 85C330 3i bios chip 80386 85C310 cache controller pipeline architecture for 80386 21U9 Text: SIS 85C310 _ Cache/Memory Controller Rev 1.1 Preliminary FEATURES • 25/33MHz Non-Pipeline Operation • Built-in Direct Mapped Cache Controller for 32K/64K/128K/256K Cache or More	OCR Scan	85C310 25/33MHz 32K/64K/128K/256K 100-Pin 80387 weitek 85C320 85C330 3i bios chip 80386 85C310 cache controller pipeline architecture for 80386 21U9	PDF
SiS 386 Abstract: 80387 386 sis weitek 85C330 sis85 Text: SIS 85C310 _ Cache/Memory Controller Rev 1.1 Preliminary FEATURES • 25/33MHz Non-Pipeline Operation • Built-in Direct Mapped Cache Controller for 32K/64K/128K/256K Cache or More	OCR Scan	85C310 25/33MHz 32K/64K/128K/256K SiS 386 80387 386 sis weitek 85C330 sis85	PDF
VL82C100 Abstract: 80386 microprocessor pin out diagram 85C330 CS97 85C320 CS9742 VL82C1 vl82c 80386 microprocessor 85C310 Text: SIS 85C320 _Bus Controller Rev 1.1 re lim in a ry FEA TU RES • Clock Generation with Software Speed Selection 1/2, 1/3 or 1/4 System Clock • AT Bus State Machine and AT bus control	OCR Scan	85C320 82C206 VL82C100 16MHz 77MHz 100-Pin 85C320 C5Q742* VL82C100 80386 microprocessor pin out diagram 85C330 CS97 CS9742 VL82C1 vl82c 80386 microprocessor 85C310	PDF
85C330 Abstract: 85C320 t23h SiS 386 Text: SIS 85C 330 _ Data Buffer Rev 1.1 Prelim inary FEATURES • Provides 32 Bits Data Buffer between CPU and 386 A T System • Provides 128 Bytes Internal Cache Memory • Bus Conversion and Swap Logic for 32 Bits, 16 Bits and 8 Bits Transfers in CPU and DMA	OCR Scan	85C330 100-Pin 85C330 128-byte -T27- -T28- 85C320 t23h SiS 386	PDF
vl82c Abstract: VL82C100 85C330 85C320 Text: SIS 85C320 Bus Controller Rev 1.1 _ Preliminary FEATURES • Clock G eneration with Software Speed Selection 1/2, 1/3 or 1/4 System Clock • AT Bus State Machine and AT bus control • Programmable Wait State G eneration: - 1 or 2 Wait State for 16 Bits Transfer	OCR Scan	85C320 82C206 VL82C100 16MHz 77MHz 100-Pin 85C320 CS267i* vl82c VL82C100 85C330	PDF