TTL 74109
Abstract: PIN CONFIGURATION 74109 853051 8530510 74LS109A
Text: 74109, LS109A Signetics Flip-Flops Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '109 is dual positive edge-triggered JK-type flip-flop featuring individual J, K, Clock, Set and Reset inputs; also com plementary Q and 5 outputs.
|
OCR Scan
|
PDF
|
LS109A
1N916,
1N3064,
500ns
500ns
TTL 74109
PIN CONFIGURATION 74109
853051
8530510
74LS109A
|
TTL 74109
Abstract: 8530510 74109 PIN CONFIGURATION 74109
Text: 74109, LS109A Signetics Flip-Flops Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 0 9 is dual positive edge-triggered JK-type flip-flop featuring individual J, K, Clock, S e t and R eset inputs; also com
|
OCR Scan
|
PDF
|
LS109A
74LS109A
33MHz
33MHz
70PULSE
500ns
500ns
1N916,
1N3064,
TTL 74109
8530510
74109
PIN CONFIGURATION 74109
|
ic 74109
Abstract: TTL 74109 PIN CONFIGURATION 74109 8 pin dip j k flipflop ic
Text: 74109 , LS109 A Signetics Flip-Flops Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION TYPE The '109 is dual positive edge-triggered JK-type flip-flop featuring individual J, K, Clock, Set and Reset inputs; also com
|
OCR Scan
|
PDF
|
LS109
74LS109A
33MHz
33MHz
N74109ll
500ns
500ns
ic 74109
TTL 74109
PIN CONFIGURATION 74109
8 pin dip j k flipflop ic
|