MOSFET B20 N03
Abstract: A09 N03 MOSFET A42 BF 331 W01 SMD mosfet lt1093 1206A102 KAT2A AVX SRDSB10PC viper 22e RAS 05 e201 siliconix
Text: OPTi Inc. OPTi 888 Tasman Drive Milpitas, CA 95035 408 486-8000 Fax: (408) 486-8001 Configuration Guide (Confidential) Product Name: Viper Xpress+ Debug Board Title: Debug Board Revision 0.0 Specification Date: January 21, 1997 Scope This document provides the specification, jumper list, rework
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PSNT21#
PSNT22#
PSNT31#
PSNT32#
MOSFET B20 N03
A09 N03 MOSFET
A42 BF 331
W01 SMD mosfet
lt1093
1206A102 KAT2A AVX
SRDSB10PC
viper 22e
RAS 05
e201 siliconix
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pin details of VIPER 22
Abstract: SDRAM DIMM 1997 SDRAM 1997 82C576 VIPer 32 opti chipset 82C579
Text: OPTi Inc. OPTi 888 Tasman Drive Milpitas, CA 95035 408 486-8000 Fax: (408) 486-8001 Application Note (OPTi Confidential) Product Name: Viper Xpress+ Chipset Title: Interfacing with Synchronous DRAM Date: January 16, 1997 Scope The Viper Xpress+ Chipset is designed to support synchronous DRAM (SDRAM). The purpose of this document is to
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82C579
82C579.
100ns
200ns
pin details of VIPER 22
SDRAM DIMM 1997
SDRAM 1997
82C576
VIPer 32
opti chipset
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Socket7
Abstract: pci pcb layout viper ide controller viper 74F244 82C576 82C578 opti opti chipset 82C579
Text: OPTi Inc. OPTi 888 Tasman Drive Milpitas, CA 95035 408 486-8000 Fax: (408) 486-8001 Application Note (OPTi Confidential) Product Name: Viper Xpress+ Chipset Title: PCB Layout Reference Guide Date: January 16, 1997 Scope This document provides the PCB (printed circuit board)
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82C576,
82C578,
82C579)
82C579
82C576:
82C579:
66MHz
33MHz
Socket7
pci pcb layout
viper
ide controller viper
74F244
82C576
82C578
opti
opti chipset
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VIPER 17H
Abstract: VIPER 27h 82c568 82C621A 486 system bus Viper 15 82C576 82C578 bios programmer 1F3H
Text: OPTi Inc. OPTi 888 Tasman Drive Milpitas, CA 95035 408 486-8000 Fax: (408) 486-8001 Application Note (OPTi Confidential) Product Name: Viper Xpress+ Chipset Title: BIOS Programming Guide Date: January 16, 1997 Scope Discussion This document outlines the recommended procedure for programming the internal registers of the Viper Xpress+ Chipset.
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