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    74S280DC Search Results

    74S280DC Datasheets (1)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74S280DC Fairchild Semiconductor 9-Bit Parity Generator / Checker Scan PDF

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    Untitled

    Abstract: No abstract text available
    Text: 280 CONNECTION DIAGRAM PINOUT A 54S/74S280 b \ l ^ ° 9-BIT PARITY GENERATOR/CHECKER DESCRIPTION — The ’280 is a high speed parity generator/checker that accepts nine bits of input data and detects whether an even or an odd number or these inputs are HIGH. If an even number of inputs are HIGH, the Sum


    OCR Scan     		PDF 54S/74S280 74S280PC 54/74S 54/47S

    54S280DM

    Abstract: 54S280FM 74S280DC 74S280FC 74S280PC
    Text: 280 C O N N E C T IO N D IA G R A M P IN O U T A 54S/74S280 b l ! ^ ° 1~4~| V c c le [ 7 9-BIT PARITY GENERATOR/CHECKER HI'S l?U n c |T jjO U Ib [ T 13 £e [T ] jÖ '2 T ]|1 2 o [I T]io GND [ 7 D E S C R IP T IO N — T he ’280 is a h ig h speed p a rity g e n e ra to r/c h e c k e r th a t


    OCR Scan     		PDF 54S/74S280 74S280PC 74S280DC 54S280DM 74S280FC 54S280FM 54/74S 54/47S 74S280PC