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    74S10 Search Results

    74S10 Result Highlights (6)

    Part ECAD Model Manufacturer Description Download Buy
    100A474S10Y Renesas Electronics Corporation 1K X 4 ECL I/O SRAM, CENT Visit Renesas Electronics Corporation
    71B74S10Y Renesas Electronics Corporation 64K(8KX8) BICEMOS SRAM Visit Renesas Electronics Corporation
    100A474S10Y8 Renesas Electronics Corporation 1K X 4 ECL I/O SRAM, CENT Visit Renesas Electronics Corporation
    10474S10DF Renesas Electronics Corporation 1K X 4 ECL I/O SRAM, CORN Visit Renesas Electronics Corporation
    100A474S10DF Renesas Electronics Corporation 1K X 4 ECL I/O SRAM, CENT Visit Renesas Electronics Corporation
    71B74S10Y8 Renesas Electronics Corporation 64K(8KX8) BICEMOS SRAM Visit Renesas Electronics Corporation
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    74S10 Price and Stock

    Rochester Electronics LLC 74S109PC

    J-K FLIP-FLOP
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    DigiKey 74S109PC Bulk 6,702 533
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    Rochester Electronics LLC 74S10PC

    IC GATE NAND 3CH 3-INP 14DIP
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    DigiKey 74S10PC Bulk 6,342 1,211
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    Rochester Electronics LLC SN74S1051N

    DIODE ARR SCHOTT 7V 50MA 16DIP
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    DigiKey SN74S1051N Bulk 5,414 128
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    Texas Instruments SN74S1051DR

    DIODE ARR SCHOTT 7V 50MA 16SOIC
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    DigiKey SN74S1051DR Cut Tape 3,132 1
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    Mouser Electronics SN74S1051DR 1,714
    • 1 $3.34
    • 10 $2.81
    • 100 $2.27
    • 1000 $1.73
    • 10000 $1.56
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    Texas Instruments SN74S1053PWR

    IC 16-BIT BUS TER ARRAY20-TSSOP
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    DigiKey SN74S1053PWR Cut Tape 2,751 1
    • 1 $2.59
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    SN74S1053PWR Reel 2,000 2,000
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    Mouser Electronics SN74S1053PWR 1,554
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    Chip1Stop SN74S1053PWR Cut Tape 2,000
    • 1 $1.97
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    • 100 $1.64
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    Find more 74S10 price and stock on Findchips.com

    74S10 Datasheets (13)

    Part ECAD Model Manufacturer Description Curated Type PDF
    74S10 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    74S10 Signetics Triple 3-Input NAND / AND Gates Scan PDF
    74S10 Signetics Triple Three-Input NAND / AND Gates Scan PDF
    74S10 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    74S109 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    74S109DC Fairchild Semiconductor Dual JK Positive Edge Triggered Flip-Flop Scan PDF
    74S109FC Fairchild Semiconductor Dual JK Positive Edge Triggered Flip-Flop Scan PDF
    74S109PC Fairchild Semiconductor Dual JK Positive Edge Triggered Flip-Flop Scan PDF
    74S109PC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74S109PCQR Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74S10DC Fairchild Semiconductor Triple 3-Input NAND Gate Scan PDF
    74S10FC Fairchild Semiconductor Triple 3-Input NAND Gate Scan PDF
    74S10PC Fairchild Semiconductor Triple 3-Input NAND Gate Scan PDF

    74S10 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: TECHNICAL DATA SHEET F 75 Ω 74S101-K100 AIRLINE PLUG/JACK All dimensions are in mm; tolerances according to ISO 2768 m-H Interface According to IEC 169-24 ; EIA-550 Documents N/A Material and plating RF_35/06.07/5.0 Connector parts Center contact Outer contact


    Original     		PDF 74S101-K100 EIA-550 D-84526 2002/95/EC

    EIA-550

    Abstract: K150 74s101
    Text: TECHNICAL DATA SHEET F 75 Ω 74S101-K150 AIRLINE PLUG/JACK All dimensions are in mm; tolerances according to ISO 2768 m-H Interface According to IEC 169-24 ; EIA-550 Documents N/A Material and plating RF_35/06.07/5.0 Connector parts Center contact Outer contact


    Original     		PDF 74S101-K150 EIA-550 D-84526 2002/95/EC EIA-550 K150 74s101

    K031

    Abstract: No abstract text available
    Text: TECHNICAL DATA SHEET F 75 Ω 74S101-K031 AIRLINE PLUG/JACK All dimensions are in mm; tolerances according to ISO 2768 m-H Interface According to IEC 169-24 ; EIA-550 Documents N/A Material and plating RF_35/06.07/5.0 Connector parts Center contact Outer contact


    Original     		PDF 74S101-K031 EIA-550 D-84526 2002/95/EC K031

    Untitled

    Abstract: No abstract text available
    Text: TECHNICAL DATA SHEET F 75 Ω 74S101-K100 AIRLINE PLUG/JACK All dimensions are in mm; tolerances according to ISO 2768 m-H Interface According to IEC 169-24 ; EIA-550 Documents N/A Material and plating RF_35/12.04/3.0 Connector parts Center contact Outer contact


    Original     		PDF 74S101-K100 EIA-550 D-84526 05-s141

    abt16244a

    Abstract: 74S1051 4kv ESD immunity
    Text: SN 74S1051 CALIFORNIA MICRO DEVICES 12-BIT SCHOTTKY BARRIER DIODE BUS TERMINATOR Features • 24 integrated diodes in a single package offers 12 channel, dual rail clamping action • Provides proper bus termination independent of external line or card loading conditions


    Original     		PDF 74S1051 12-BIT 16-pin ABT16244A abt16244a 74S1051 4kv ESD immunity

    K031

    Abstract: No abstract text available
    Text: TECHNICAL DATA SHEET F 75 Ω 74S101-K031 AIRLINE PLUG/JACK All dimensions are in mm; tolerances according to ISO 2768 m-H Interface According to IEC 169-24 ; EIA-550 Documents N/A Material and plating RF_35/12.04/3.0 Connector parts Center contact Outer contact


    Original     		PDF 74S101-K031 EIA-550 D-84526 05-s141 K031

    Untitled

    Abstract: No abstract text available
    Text: SN 74S1051 CALIFORNIA MICRO DEVICES 12-BIT SCHOTTKY BARRIER DIODE BUS TERMINATOR Features • 24 integrated diodes in a single package offers 12 channel, dual rail clamping action • Provides proper bus termination independent of external line or card loading conditions


    Original     		PDF 74S1051 12-BIT 16-pin impro02mm) UL94V-0

    Untitled

    Abstract: No abstract text available
    Text: TECHNICAL DATA SHEET F 75 Ω 74S101-K150 AIRLINE PLUG/JACK All dimensions are in mm; tolerances according to ISO 2768 m-H Interface According to IEC 169-24 ; EIA-550 Documents N/A Material and plating RF_35/12.04/3.0 Connector parts Center contact Outer contact


    Original     		PDF 74S101-K150 EIA-550 D-84526 05-s141

    Untitled

    Abstract: No abstract text available
    Text: 74S1051 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003 D D D D, N, NS, OR PW PACKAGE TOP VIEW Designed to Reduce Reflection Noise Repetitive Peak Forward Current to 200 mA 12-Bit Array Structure Suited for


    Original     		PDF SN74S1051 12-BIT SDLS018B

    Untitled

    Abstract: No abstract text available
    Text: C A LIFO RN IA M IC R O DEVICES S N 74S1051 ►► ► ► ► 12-BIT SCHO TTKY BARRIER DIO DE BUS TER M IN A TO R F eatu res Applications • • • • • • 24 integrated diodes in a single package offers 12 channel, dual rail clam ping action Provides proper bus term ination independent o f


    OCR Scan     		PDF 74S1051 12-BIT 16-pin

    CI 7474

    Abstract: CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 fairchild 9024 ci 74LS74 74ls107
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 ui 9 D UJ 5 -=pi (3 J Q 2 — J SD 0 CP Z o (3 11 4 K Ä 0 Co “LT in > _6 12 CP 3 -0 14 K Co ° 7 o-i- CP 13 —c K Cd °


    OCR Scan     		PDF 54S/74S109, 54LS/74LS109 54H/74H74, 54S/74S74, 54LS/74LS74 54H/74H73, 54LS/74LS279 93L14 54LS/74LS196 54LS/74LS197 CI 7474 CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 fairchild 9024 ci 74LS74 74ls107

    NAND Gate 3-Input 7410

    Abstract: 74LS10PC
    Text: 10 CO NNECTIO N DIAGRAMS PINO UT A '''54/7410 ^é4H/74H10 ^54S/74S10 ö / ' o -h? ^ 4 L S /7 4 L S 1 0 ^ / y 7 TRIPLE 3-INPUT NAND GATE ORDERING CODE: See Section 9 PIN PKGS OUT CO M M ERCIAL GRADE M ILITARY GRADE V cc = +5.0 V ±5%, T a = 0° C to +70° C


    OCR Scan     		PDF 4H/74H10 54S/74S10 7410PC, 74H10PC 74S10PC, 74LS10PC 7410DC, 74H10DC 74S10DC, 74LS10DC NAND Gate 3-Input 7410

    IC 7410

    Abstract: 7410 JRC IC 7430 IC 7420 IC 7400 nand OF IC 7410 7410 ic ls 7400 hc 7400 7410 1c
    Text: - 25- Triple 3 Input NAND 7410 Vcc 1C IV ac 38 3A 3Y ninininiLriiniriif ft IB 2A 2B 2C 2Y GND O Y = A •B •C 74S10 N LS ALS ALSK F S AS AC max L-*H T 22 15 11 8 6 4.5 4.5 11.1 12. 3,24 30 ns tpd max H—»L 1 15 15 10 7 5. 3 5 4.5 11.1 12.3 24 30 ins IN


    OCR Scan     		PDF

    TTL 74ls74

    Abstract: 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 5 ui 9 D UJ -=pi (3 J Q 2 — J SD 0 CP Z o (3 4 K Ä Co “LT in > </> O a 3 -0 K Co ° I- 3 a. I- 3 O 4-0 Co ? 15 D61 54/7474, 54H/74H74,


    OCR Scan     		PDF 54S/74S109, 54LS/74LS109 54H/74H74, 54S/74S74, 54LS/74LS74 54H/74H73, 54H/74H73 54H/74H103 54S/74S113 54LS/74LS113 TTL 74ls74 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN

    TTL 7411

    Abstract: PIN CONFIGURATION 7410 74LS11 function table TTL LS 7411 74 LS 00 Logic Gates LS 7411 74LS10 pin configuration TTL 7410 TTL 7410 AND propagation delay PIN CONFIGURATION 74ls10
    Text: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND '10 , AND ('11) Gates Product Specification I TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns 11mA


    OCR Scan     		PDF 74LS10 74S10 74LS11 74S11 N7410N, N74LS10N, N74S10N N7411N, N74LS11N, N74S11N TTL 7411 PIN CONFIGURATION 7410 74LS11 function table TTL LS 7411 74 LS 00 Logic Gates LS 7411 74LS10 pin configuration TTL 7410 TTL 7410 AND propagation delay PIN CONFIGURATION 74ls10

    TTL 74ls74

    Abstract: 7474 14 PIN 74ls76 7476 ttl ttl 74ls109 74LS107 74LS73 74ls74 TTL 74ls76 74LS109
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL M A S T E R /S LA V E E D G E -T R IG G E R E D D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 ui 9 D UJ 5 -=pi J Q (3 CP o K Z 2 — J SD 0 _6 Co (3 “LT in > z o Q J CP I- 3 a. 3 O So J - Ö K 4-0


    OCR Scan     		PDF 54S/74S109, 54LS/74LS109 54H/74H74, 54S/74S74, 54LS/74LS74 54H/74H73, 54L15 TTL 74ls74 7474 14 PIN 74ls76 7476 ttl ttl 74ls109 74LS107 74LS73 74ls74 TTL 74ls76 74LS109

    CI 7410

    Abstract: CI 74ls10 74LS10 74LS10 pin configuration N7410F N7410N N74H10F N74H10N N74LS10F N74LS10N
    Text: PIN CONFIGURATIONS 54/7410 54H/74H10 54S/74S10 54LS/74LS10 ORDERING CODE See Section 9 for further Package and Ordering Information. Œ *14*] VCC Œ E m m m [I 2Sl Œ 3 Œ PACKAGES C O M M E R C IA L RANGES to »70"C PIN CONF. VCC - 5V * 5"/o; T a = 0°C


    OCR Scan     		PDF 54H/74H10 54S/74S10 54LS/74LS10 N7410N N74H10N N74S10N N74LS10N N7410F N74H10F N74S10F CI 7410 CI 74ls10 74LS10 74LS10 pin configuration N7410F N7410N N74LS10F N74LS10N

    TTL 7410

    Abstract: ua 7411 PIN CONFIGURATION 7410 PIN CONFIGURATION 7411 TTL 7411 74LS10 pin configuration 7411 pin configuration 74LS11 function table 74ls 7410 pin configuration
    Text: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products • Triple Three-Input NAND ’10 , AND ('11) Gates Product Specification TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns


    OCR Scan     		PDF 74LS10 74S10 74LS11 74S11 N7410N, N74LS10N, N74S10N N7411N, N74LS11N, N74S11N TTL 7410 ua 7411 PIN CONFIGURATION 7410 PIN CONFIGURATION 7411 TTL 7411 74LS10 pin configuration 7411 pin configuration 74LS11 function table 74ls 7410 pin configuration

    Untitled

    Abstract: No abstract text available
    Text: GD54/74S10 TRIPLE 3-INPUT POSITIVE NAND GATES Description Pin Configuration This device contains three independent 2-input NAND gates. It performs the Boolean functions Y = A .B .C or Y=A+"BVC in positive logic. Vcc m 1C hi 1Y 3C 3B n^i rn h°ì 3A fi 3Y rn


    OCR Scan     		PDF GD54/74S10

    LM 7410

    Abstract: No abstract text available
    Text: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND ’10 , AND ('11) Gates Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns


    OCR Scan     		PDF 74LS10 74S10 74LS11 74S11 N7410N, N74LS10N, N74S10N N7411N, N74LS11N, N74S11N LM 7410

    ABT16244A

    Abstract: No abstract text available
    Text: CALIFO RN IA M IC R O DEVICES SN 74S1051 ►► ► ►► 12-BIT S C H O TT KY BARRIER DIODE BUS TER M IN A TO R F e a tu re s A pplications • • • • • • 2 4 in te g ra te d diodes in a single package offers 12 channel, dual rail cla m p in g a ctio n


    OCR Scan     		PDF 74S1051 12-BIT 16-pin UL94V-0 ABT16244A

    74LS109D

    Abstract: 4151 cp IR 9024 74LS109PC 74S109
    Text: I 1 NATIONAL SEMICOND -CLOGIO OSE D 1 5 0 1 1 5 2 □Dt,37flS 1 | T~ ¥ 6 - 0 7 - 0 7 109 C O N N E C T IO N D IA G R A M P IN O U T A 54S/74S109 54LS/74LS109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP D E S C R IP T IO N — T he ’109 co n sists of two high speed, com pletely indepen­


    OCR Scan     		PDF 37flS 54S/74S109 54LS/74LS109 54/74S 54/74LS 74LS109D 4151 cp IR 9024 74LS109PC 74S109

    74S206

    Abstract: 74s201
    Text: 54/74S ELECTRICAL CHARACTERISTICS See Notes - Page 50 INPUT VOLTAGE V|L (V) PARAMETER TEST CONDITIONS LOW LEVEL VÇC~MIN MIN TYP MAX OUTPUT VOLTAGE V|C(V) V|H (V) HIGH LEVEL CLAMP VOLTAGE V çç= M IN VCC = “ IN l|=-18 mA MIN TYP MAX MIN TYP VOH (V) HIGH LEVEL


    OCR Scan     		PDF 54/74S 54/74S00 54/74S02 54/74S03 54/74S04 54/74S05 54/74S260 54/74S280 54/74S301 74S206 74s201

    74S107

    Abstract: No abstract text available
    Text: BiCMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM IDT71B74 In te g ra te d D evice T ec hnology, In c . FEATURES: DESCRIPTION: • H igh-speed ad dress to M A TC H com parison tim e — C om m ercia l: 8/1 0/12 /15/20ns (m ax.) • H igh-speed ad dress acce ss tim e


    OCR Scan     		PDF IDT71B74 /15/20ns 6/7/8/10ns 28-pin 28-pi-7 T71B74 74S107