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    74LS13 Search Results

    74LS13 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74LS132FPEL-E Renesas Electronics Corporation HD74LS Series Visit Renesas Electronics Corporation
    74LS139FPEL-E Renesas Electronics Corporation HD74LS Series Visit Renesas Electronics Corporation
    74LS132P-E Renesas Electronics Corporation HD74LS Series Visit Renesas Electronics Corporation
    74LS138P-E Renesas Electronics Corporation HD74LS Series Visit Renesas Electronics Corporation
    74LS139P-E Renesas Electronics Corporation HD74LS Series Visit Renesas Electronics Corporation
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    74LS13 Price and Stock

    Rochester Electronics LLC SN74LS132NS

    IC GATE NAND 4CH 2-INP 14-SO
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    DigiKey SN74LS132NS Bulk 18,900 761
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    Rochester Electronics LLC SN74LS132NSR

    IC GATE NAND 4CH 2-INP 14SO
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    DigiKey SN74LS132NSR Bulk 16,000 702
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    Rochester Electronics LLC 74LS139FPEL-E

    DUAL 2-TO-4-LINE DECODERS/DEMUXS
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    DigiKey 74LS139FPEL-E Bulk 8,000 508
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    Rochester Electronics LLC 74LS132P-E

    IC NAND QUAD 2-INP
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    DigiKey 74LS132P-E Bulk 7,900 339
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    Rochester Electronics LLC SN74LS132MR1

    IC SCHMITT TRIGGER QUAD
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    DigiKey SN74LS132MR1 Bulk 7,000 1,665
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    74LS13 Datasheets (66)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74LS13 Motorola SCHMITT TRIGGERS DUAL GATE/HEX INVERTER Original PDF
    74LS13 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    74LS13 Raytheon Schmitt-Trigger Positive-NAND Gates and Inverters with Totem-Pole Outputs Scan PDF
    74LS13 Signetics Dual 4-Input NAND Schmitt Trigger Scan PDF
    74LS13 Signetics Dual 4-input NAND Schmitt Trigger Scan PDF
    74LS13 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    74LS132 Fairchild Semiconductor Quad 2-Input NAND Gate with Schmitt Trigger Input Original PDF
    74LS132 Hitachi Semiconductor Quadruple 2-input Positive NAND Schmitt-triggers Original PDF
    74LS132 Motorola QUAD 2-INPUT SCHMITT TRIGGER NAND GATE Original PDF
    74LS132 On Semiconductor LOW POWER SCHOTTKY Original PDF
    74LS132 Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND SCHMITT TRIGGERS Original PDF
    74LS132 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    74LS132 Raytheon Quad 2-lnput Schmitt-Trigger Scan PDF
    74LS132 Signetics Quad 2-Input NAND Schmitt Trigger Scan PDF
    74LS132 Signetics Quad 2-input NAND Schmitt Trigger Scan PDF
    74LS132 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    74LS132A Signetics Quad 2-Input NAND Schmitt Trigger / 13 Input NAND Gate Scan PDF
    74LS132DC Fairchild Semiconductor Quad 2-Input Schmitt Trigger NAND Gate Scan PDF
    74LS132F Signetics Quad 2-Input NAND Schmitt Trigger / 13 Input NAND Gate Scan PDF
    74LS132FC Fairchild Semiconductor Quad 2-Input Schmitt Trigger NAND Gate Scan PDF

    74LS13 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    TTL 74ls133

    Abstract: 74ls133 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
    Text: SN54/74LS133 13-INPUT NAND GATE 13-INPUT NAND GATE VCC 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 GND LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN


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    PDF SN54/74LS133 13-INPUT 751B-03 SN54LSXXXJ SN74LSXXXN SN74LSXXXD TTL 74ls133 74ls133 SN54LSXXXJ SN74LSXXXD SN74LSXXXN

    74LS13

    Abstract: 74LS14 751A-02 trigger schmitt 74 14 ttl 74ls14
    Text: SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The SN54LS / 74LS13 and SN54LS / 74LS14 contain logic gates / inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into


    Original
    PDF SN54/74LS13 SN54/74LS14 SN54LS 74LS13 74LS14 751A-02 trigger schmitt 74 14 ttl 74ls14

    M74LS136P

    Abstract: 20-PIN MITSUBISHI ELECTRIC SEMICONDUCTOR
    Text: MITSUBISHI LSTTLs M 74LS136P QUADRUPLE 2 -IN P U T EXC LU SIVE OR GATES W IT H OPEN COLLECTOR O UTPU TS DESCRIPTION The M 74LS 136P containing 4 is a semiconductor integrated circuit dual-input exclusive-OR gates w ith PIN CONFIGURATION TOP VIEW open collector output.


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    PDF M74LS136P M74LS136P 16-PIN 20-PIN MITSUBISHI ELECTRIC SEMICONDUCTOR

    ATML U 010

    Abstract: ATML H 010 1S2074 400M 74LSOO HD74LS139 OG-16 L400M ATML 010
    Text: H D 74LS139. Dual 2-line-to-4-line Decoders/Demultiplexers IPIN ARRANGEMENT The H 74LS139 comprises two individual two-line-to-fourline decoder in a single package. The active-low enable input can be used as a data line in demultiplexing applications. IBLOCK DIAGRAM


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    PDF HD74LS139 QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 ATML U 010 ATML H 010 1S2074 400M 74LSOO OG-16 L400M ATML 010

    DDR Schaltkreise

    Abstract: DL014D DL132D 74LS132N Deutschen Demokratischen Republik DSAGER00016 74ls014 26713
    Text: inn]D[klP3is ] ^ i0 ^ ^ 3 ls,Q n S ' DL 014 D DL 132 D Internationale Vergleichstypen; SN 74L S 014 N SN 74LS132 N Schaltkreise in Low -pow er-S chottky-Tschnologie DL 0 14 D 6 Schm itt-Trigger-Inverter Y = Ä DL 132 D 4 S chm itt-Trigger NAND-Gatter m it je 2 Eingängen


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    PDF 74LS132 DDR Schaltkreise DL014D DL132D 74LS132N Deutschen Demokratischen Republik DSAGER00016 74ls014 26713

    74191 8 bit

    Abstract: 7443 Flip-Flop D134 7443 d Flip-Flop 74LS42 74155 9B23 D135 93L38 93L11
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8


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    PDF 74LS190 74LS191 93L21, 54/74S139, 54LS/74LS139 54LS/74LS155 54LS/74LS156 93L01, 93L34, 54LS/74LS259 74191 8 bit 7443 Flip-Flop D134 7443 d Flip-Flop 74LS42 74155 9B23 D135 93L38 93L11

    74LS190 PIN diagram

    Abstract: ttl 7442 74LS42 74LS138 pin diagram D134 7442 pin diagram 74155 74145 D133 93L01
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8


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    PDF 74LS190 74LS191 93L21, 54/74S139, 54LS/74LS139 54LS/74LS155 54LS/74LS156 93L01, 93L34, 54LS/74LS259 74LS190 PIN diagram ttl 7442 74LS42 74LS138 pin diagram D134 7442 pin diagram 74155 74145 D133 93L01

    7448 decoder

    Abstract: ID 9302 Fairchild 74190 pin diagram decoder 7447 TTL 7448 74LS47 74LS47 pin TTL 7446 decoder 74LS47 decoder 7448
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 G N D = Pin 8 Vcc = Pin 16 G N D = Pin 8


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    PDF 74LS190 74LS191 93L21, 54/74S139, 54LS/74LS139 54LS/74LS155 54LS/74LS156 93L01, 93L34, 54LS/74LS259 7448 decoder ID 9302 Fairchild 74190 pin diagram decoder 7447 TTL 7448 74LS47 74LS47 pin TTL 7446 decoder 74LS47 decoder 7448

    transistor d133

    Abstract: Decoder BCD 7 seg ttl 7442 transistor 6B 7-seg ANODE COMMON 74155 74LS247 pin diagram of 74LS247 ttl 74191 75491
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8


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    PDF 74LS190 74LS191 93L21, 54/74S139, 54LS/74LS139 54LS/74LS155 54LS/74LS156 93L01, 93L34, 54LS/74LS259 transistor d133 Decoder BCD 7 seg ttl 7442 transistor 6B 7-seg ANODE COMMON 74155 74LS247 pin diagram of 74LS247 ttl 74191 75491

    TTL LS 7406

    Abstract: el 7406 74l804 ls 7404 7404 ls 74114 ic 74132 IC 7404 IC TTL 7402 TTL IC 7405
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D7 54/7430, 54H/74H30 54S/74S30, 54LS/74LS30 Vcc NC r r r NC r D8 54S/74S133, 54LS/74LS133 Vcc NC r fi fi Ili ill HI Li Lil lil GND LzJ R R R R F IR R F I Vcc E RRRRRRRFl LiJ ikj Lil l±J UJ LsJ IzJ GND LU D11


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    PDF 54H/74H30 54S/74S30, 54LS/74LS30 54S/74S133, 54LS/74LS133 54S/74S134 54S/74S02, 54LS/74LS02, 54LS/74LS28 74LS33 TTL LS 7406 el 7406 74l804 ls 7404 7404 ls 74114 ic 74132 IC 7404 IC TTL 7402 TTL IC 7405

    Untitled

    Abstract: No abstract text available
    Text: 74LS136 LS TTL DN74LS Series 74LS136 Quad 2 - input E xclusive OR G ates with Open C ollector Outputs • Description P-1 DN 74LS136 contains four 2-input exclusive OR gate circuits w ith open collector outputs. ■ • • • • Features “Wired” AND capability


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    PDF DN74LS136 DN74LS 74LS136

    Untitled

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series 74LS139 74LS139 Dual 2 -lin e to 4 -lin e Decoders / Demultiplexers H Description P -2 D N 74LS139 contains tw o 2-bit binary to quaternary de­ coder/dem ultiplexer circuits, each w ith independent enable input term inals. • Features


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    PDF DN74LS DN74LS139 74LS139 16-pin

    Untitled

    Abstract: No abstract text available
    Text: Am25LS138 • Am54LS/74LS138 3-Line To 8-Line Decoder/Demultiplexer D IS T IN C T IV E C H A R A C T E R IS T IC S L O G IC D IA G R A M • Inverting and non-inverting enable inputs • A m 2 5 L S devices offer the following improvements over Am 54/74LS


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    PDF Am25LS138 Am54LS/74LS138 54/74LS Am25LS/54 LS/74LS138

    Untitled

    Abstract: No abstract text available
    Text: GD54/74LS139 DUAL 2-TO-4-LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration • • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems Schottky Clamped for High Performance Vçç SELECT DATA OUTPUTS ENABLE^_ _


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    PDF GD54/74LS139

    SP74SC139N

    Abstract: 74ls139 decoder pin configuration 74LS139 SP74SC139F E332A
    Text: / SP74SC139 DECODER/DEMULTIPLEXER PIN CO NFIGURATIO N 1G [ T v cc 1A [T Ï3 2G FEATURES • Designed for high performance memory decoders in microprocessor sytems ■ Two independent 2 to 4 line Decoders/ Demultiplexers with inverted outputs ■ Pin compatible with 74LS139


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    PDF SP74SC139 74LS139 SP74SC139 74LS139. SP74SC139N 74ls139 decoder pin configuration 74LS139 SP74SC139F E332A

    74LS137

    Abstract: SP74SC137F SP74SC137N
    Text: SP7 4 S C 1 3 7 S DECODER/DEMULTIPLEXER P I PIN CONFIGURATIO N FEATURES C • Designed for high performance memory decoders in microprocesor systems ■ 3 to 8 line decoders 3 enable inputs and inverted outputs with latches ■ Pin com patible with 74LS137


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    PDF SP74SC137 74LS137 SP74SC137 74LS137. 74LS137 SP74SC137F SP74SC137N

    74LS139

    Abstract: 74l513 demultiplexer 74ls 74ls signetics pin diagram of 74LS 74LS 74S139 93L21 N74LS139D N74LS139N
    Text: 74LS139, S139 Signetics Decoders/Demultiplexers Dual 1-of-4 D e c o d e r/D e m u ltip le x e r Product Specification Logic Products FEATURES • Demultiplexing capability • Two independent 1-of-4 decoders • Multifunction capability • Replaces 9321 and 93L21 for


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    PDF 93L21 74LS139, TYPICS139, 1N916, 1N3064, 500ns 74LS139 74l513 demultiplexer 74ls 74ls signetics pin diagram of 74LS 74LS 74S139 N74LS139D N74LS139N

    74ls138 truth table

    Abstract: 74LS138 74 LS 138 DECODER connection for 74LS138 74LS138 3 to 8 decoder Pin demultiplexer 3 to 8 truth table 74ls138 demultiplexer LS138 LOGIC OF 74LS138 of 74LS138 3 to 8 decoder
    Text: g MOTOROLA SN54/74LS138 1-0F-8 DECODER/ DEMULTIPLEXER The LSTTL/MSI SN54/74LS138 is a high speed 1-of-8 Decoder/ Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel ex­


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    PDF SN54/74LS138 1-of-24 LS138 1-of-32 LS138s SN54/74LS138 74ls138 truth table 74LS138 74 LS 138 DECODER connection for 74LS138 74LS138 3 to 8 decoder Pin demultiplexer 3 to 8 truth table 74ls138 demultiplexer LOGIC OF 74LS138 of 74LS138 3 to 8 decoder

    IC 74LS14

    Abstract: 74ls14 74LSxx ic 74ls13
    Text: M OTOROLA SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The S N 54LS /74LS 13 and SN 54LS /74LS 14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into


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    PDF /74LS SN54/74LS13 SN54/74LS14 IC 74LS14 74ls14 74LSxx ic 74ls13

    74LS132

    Abstract: No abstract text available
    Text: MOTOROLA SN54/74LS132 QUAD 2-INPUT SCHMITT TRIGGER NAND GATE The S N 54/74LS 132 contains four 2-Input NAND Gates which accept stan­ dard TTL input signals and provide standard TTL output levels. They are ca­ pable of transforming slowly changing input signals into sharply defined, jitterfree output signals. Additionally, they have greater noise margin than


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    PDF SN54/74LS132 54/74LS SN54/74LS132 74LS132

    Untitled

    Abstract: No abstract text available
    Text: <8 > M OTOROLA SN54/74LS133 mrnirnmrrirnram -1 r u w -1 u 1 13-1NPUT NAND GATE 1 Ù L ìJ L ì J L L J I Ì J L l I LO W POW ER SCH O TTK Y J Suffix — Case 620-09 Ceramic N Suffix — Case 648-08 (Plastic) GUARANTEED OPERATING RANGES S YM B O L PARAMETER


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    PDF SN54/74LS133 13-1NPUT

    74LS133

    Abstract: truth table NOT gate 74
    Text: M MOTOROLA SN54/74LS133 13-INPUT NAND GATE 13-IN P U T NAND GATE VCC MRrïïirïïiRirïïir^im LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 L U L iJ ll J L i J L i J L iJ LULjJ GND N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 5 ORDERING INFORMATION


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    PDF SN54/74LS133 13-INPUT 13-IN 751B-03 SN54LSXXXJ SN74LSXXXN SN74LSXXXD SN54/74LS133 74LS133 truth table NOT gate 74

    74LS137

    Abstract: aag2
    Text: <8> M O TO R O LA SN54/74LS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES LOW POWER SCHOTTKY DATA OUTPUTS VCC YÛ Y1 Y2 Y3 Y4 Y5 Y6 pisi |~i?1 |~ÌT| HT! fiil f~M~| [~iÖ1 [~9~|


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    PDF SN54/74LS137 751B-03 SN54LSXXXJ SN74LSXXXN SN74LSXXXD 74LS137 aag2

    Untitled

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series 74LS13 74LS13 &MHIS13 Dual 4 -input P o sitiv e NAND S ch m itt-T riggers H D escription P-1 DN 74LS13 contains tw o 4-input positive isolation NAND circuits w ith Schm itt triggers. • Features • • • • • Ideal for w aveform shaping


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    PDF DN74LS DN74LS13 14-pin SO-14D) MA161.