Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    74LS TTL SERIES Search Results

    74LS TTL SERIES Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74LS652NS Rochester Electronics LLC 74LS652 - Registered Bus Transceiver, F/FAST Series, 1-Func, 8-Bit, True Output, TTL Visit Rochester Electronics LLC Buy
    74LS12N Rochester Electronics LLC 74LS12 - NAND Gate, LS Series, 3-Func, 3-Input, TTL, PDIP14 Visit Rochester Electronics LLC Buy
    74LS190N Rochester Electronics LLC 74LS190 - Decade Counter, Synchronous, Bidirectional, TTL, PDIP16 Visit Rochester Electronics LLC Buy
    74LS384N Rochester Electronics LLC 74LS384 - Multiplier, LS Series, 8-Bit Visit Rochester Electronics LLC Buy
    PQU650M-F-COVER Murata Manufacturing Co Ltd PQU650M Series - 3x5 Fan Cover Kit, RoHs Medical Visit Murata Manufacturing Co Ltd

    74LS TTL SERIES Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    octal Bilateral Switches

    Abstract: MM74HC14M MM74HC138M CD4025BCM MM74HC00M MM74HC74AM MM74HC125M MM74HC04M cd4046bcm cd4052bcm
    Text: 1/3 CMOS LOGIC MM74HC SERIES MM74HCT/U SERIES • HIGH SPEED CMOS TECHNOLOGY, CMOS DRIVE LEVELS, SPEED COMPARABLE TO 74LS SERIES Part Number Description • HIGH SPEED CMOS TECHNOLOGY, TTL DRIVE LEVELS, SPEED COMPARABLE TO 74LS SERIES SQP £ ea. Gates & Inverters


    Original     		MM74HC MM74HC00M MM74HC02M MM74HC04M MM74HC08M MM74HC14M MM74HC32M MM74HC86M MM74HC132M MM74HC74AM octal Bilateral Switches MM74HC138M CD4025BCM MM74HC125M cd4046bcm cd4052bcm PDF

    74LS series logic gates 3 input or gate

    Abstract: 74LS series logic gates 74LS series logic gate symbols 74ls gate symbols 74125 ic 74LS126 74LS55 r025 74LS125 74LS51
    Text: FAIRCHILD DIGITAL TTL High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram 2 High Speed 54H/74H 6 ns/22 mW Std. TTL 9N 54/74 10 ns/10 mW Low Power Schottky 54LS/74LS 5 ns/2 mW Item 9000 Series 8 ns/10 mW (Cont'd) Function’11 SSI FUNCTIONS 5 't/I


    OCR Scan     		ns/10 54LS/74LS 54H/74H ns/22 54S/74S ns/19 74LS266 54H/74H52 54H/74H50 74LS series logic gates 3 input or gate 74LS series logic gates 74LS series logic gate symbols 74ls gate symbols 74125 ic 74LS126 74LS55 r025 74LS125 74LS51 PDF

    74ls series logic family

    Abstract: SN74HC logic family CMOS 4000 TTL 74ALS CMOS 4000 Series family cmos logic 4000 series 74LS TTL 245 74ls TTL family 74ls series family cross reference cmos 4000
    Text: INTEGRAL KOREA Cross Reference Characteristics Technology IK Semi Hitachi IN74 TTL CMOS 4000 On Semi Toshiba TI Philips Fairchild SN74 SN74 SN74 74 DM74 IN74LS HD74LS SN74LS SN74LS SN74LS 74LS DM74LS IN74ALS HD74ALS SN74ALS SN74ALS SN74ALS 74ALS DM74ALS IW4


    Original     		HD74LS SN74LS DM74LS IN74ALS HD74ALS SN74ALS 74ls series logic family SN74HC logic family CMOS 4000 TTL 74ALS CMOS 4000 Series family cmos logic 4000 series 74LS TTL 245 74ls TTL family 74ls series family cross reference cmos 4000 PDF

    cmos logic 4000 series

    Abstract: TTL 74ALS 74 series TTL NOT gate MM74HC CMOS 4000 Series family 74ls series logic family CMOS 4000 SN74HC logic family 74ls TTL family 74ALS
    Text: z Cross Reference Characteristics Technology IK Semi Hitachi IN74 TTL CMOS 4000 On Semi Toshiba TI Philips Fairchild SN74 SN74 SN74 74 DM74 IN74LS HD74LS SN74LS SN74LS SN74LS 74LS DM74LS IN74ALS HD74ALS SN74ALS SN74ALS SN74ALS 74ALS DM74ALS IW4 HD14 MC14 TC4


    Original     		HD74LS SN74LS DM74LS IN74ALS HD74ALS SN74ALS cmos logic 4000 series TTL 74ALS 74 series TTL NOT gate MM74HC CMOS 4000 Series family 74ls series logic family CMOS 4000 SN74HC logic family 74ls TTL family 74ALS PDF

    LDT1

    Abstract: No abstract text available
    Text: Plastic Fiber Optical Data Link LD Series •Features 1. Low pulse width distortion. 2. This is a TTL and CMOS compatible interface. Direct coupling permitted to 74LS and 74HC 3. Full-lock connectors in which the optical connectors use a lock lever in the


    Original     		PDF

    DN74LS245

    Abstract: No abstract text available
    Text: DN74LS245 LS TTL DN74LS Series DN74LS245 ro 74LS^4-S' Octal Bus Transceivers with 3 -state Outputs P-3 • Description DN74LS245 contains eight bus transmitter/receiver circuits with non-inverted outputs. ■ Features • Bidirectional transfer or separation capability for two 8-bit


    OCR Scan     		DN74LS DN74LS245 400mV -15mA) PDF

    Z427

    Abstract: FL 9014 TTL 7409 TTL 7486 74LS32 74ls86 TTL 74s32 74LS08 74LS11 74LS02
    Text: FAIRCHILD DIGITAL TTL SSI FUNCTIONS Cont’d X to x n agic/Conne Diagram igh Speed 54H/74H ns/22 mW O IO U) —1 ligh Speed Schottky 54S/74S ns/19 mW CO Std. TTL 54/74 1 ns/10 mW E a> Dw Power Schottky ILS/74LS ns/2 mW ~'c o u c 3 U. 9000 Series ns/10 mW


    OCR Scan     		ns/10 54S/74S ns/19 54H/74H ns/22 ILS/74LS 54LS/74LS02 54S/74S02 54LS/74LS27 Z427 FL 9014 TTL 7409 TTL 7486 74LS32 74ls86 TTL 74s32 74LS08 74LS11 74LS02 PDF

    74LS08 Quad 2-Input AND Gates

    Abstract: TTL 74s32 TTL 7408 or 2 input 74Ls32 74LS11 and 74LS32 74ls32 quad 2-input OR gates 54LS TTL 7421 74LS 3-input NOR 74LS11
    Text: FAIRCHILD DIGITAL TTL High Speed 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram'2’ E £ Std. TTL 54/74 10 ns/10 mW ~c o o c S U. Low Power Schottky 54LS/74LS 5 ns/2 mW Cont’d 9000 Series 8 ns/10 mW SSI FUNCTIONS 5


    OCR Scan     		ns/10 54H/74H ns/22 54S/74S ns/19 54LS/74LS 54LS/74LS02 54LS/74LS27 54LS/74LS260 74LS08 Quad 2-Input AND Gates TTL 74s32 TTL 7408 or 2 input 74Ls32 74LS11 and 74LS32 74ls32 quad 2-input OR gates 54LS TTL 7421 74LS 3-input NOR 74LS11 PDF

    Altera EP1800

    Abstract: EP1800 JEDEC FORMAT EP1800 altera logicaps TTL library SCHEMA PA BUILT UP EP1800 LOGIC DIAGRAM ep18001
    Text: EP1800 Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conventional and custom logic. Speed equivalent to 74LS TTL with 25 MHz clock rates. “Zero Power” typically 10/jA standby . Active power of 250 mW at 5 MHz.


    OCR Scan     		EP1800 Altera EP1800 EP1800 JEDEC FORMAT EP1800 altera logicaps TTL library SCHEMA PA BUILT UP EP1800 LOGIC DIAGRAM ep18001 PDF

    FZH115B

    Abstract: fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104
    Text: Digital I.C.s, 74INTEGRATED CIRCUITS DIGITAL TTL, 74LS & 74HC Series Quad 2-input NAND gate Quad 2-input NAND gate, open collector Quad 2-input NOR gate Quad 2-input NOR gate, open collector Hex inverter Hex inverter, O/C collector Hex inverter, Buffer 30V O/P


    Original     		74INTEGRATED Line-to-10 150ns 16-DIL 150ns 18-pin 250ns 300ns FZH115B fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104 PDF

    DN74LS290

    Abstract: QD32
    Text: LS TTL DN74LS Series DN74LS290 DN74LS290 N>74LSÌ.<ÌO Decade Counters • Description P-1 D N 74LS290 is an asynchronous decade counter w ith a directcoupled reset in p u t and nine direct-coupled set inputs. ■ Features • • • • • Direct-coupled reset input


    OCR Scan     		DN74LS DN74LS290 DN74LS290 42MHz 14-pin. trS15ns, QD32 PDF

    shiftregisters

    Abstract: EP910 altera TTL library 74LS series logic gates 74LS EP1810 EP1810-45 EP610 PLE40 altera logicaps TTL library
    Text: EP1810 Y 7 \ m HIGH PERFORMANCE 4 8 MACROCELL EPLD m 10 I U FEATURES GENERAL DESCRIPTION • Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conven­ tional and custom logic. • Speed equivalent to 74LS TTL with 33 MHz clock


    OCR Scan     		PDF

    Untitled

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series D N 74LS 136 DN74LS136 ro 7q. LS 2>£> Quad 2 - input E xclusive OR G ates with Open C ollector Outputs) • Description P-1 DN74LS136 contains four 2-input exclusive OR gate circuits w ith open collector o utputs. ■ Features • •


    OCR Scan     		DN74LS DN74LS136 DN74LS136 14-pin SO-14D) S15ns, PDF

    DN74LS113

    Abstract: MA161 100 mhz trigger generator 0n74
    Text: I DN74LS113 LS TTL DN74LS Series D N 74LS 113 Dual J-K Negative Edge-Triggered F lip -F lop s with Set I Description P-1 DN74LS113 contains two negative-edge triggered J-K flip­ flop circuits, each with independent clock-CP, J, K, and direct-coupled set input terminals.


    OCR Scan     		0N74LS DN74LS113 DN74LS113 14-pin SO-14D) trS15ns. MA161 100 mhz trigger generator 0n74 PDF

    Untitled

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series DN74LS95B DN74LS95B f^74ls?Sß 4-bit Parallel - Access Shift Registers • Description P-1 DN74LS95B is a 4-bit serial/parallel input to serial/parallel o u tp u t shift register. ■ Features • • • • • S ynchronous serial/parallel input to serial/parallel o u tput


    OCR Scan     		DN74LS DN74LS95B DN74LS95B 14-pin PDF

    Untitled

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series DN74LS393 DN74LS393 K>74LS Dual 4 - b i t Binary Counters • Description P-1 DN 74LS393 contains tw o asynchronous 4-bit binary hexa­ decim al co u n ter circuits w ith direct-coupled reset inputs. ■ Features • • • • Two circuits corresponding to LS93 and LS293 for high


    OCR Scan     		DN74LS DN74LS393 DN74LS393 74LS393 LS293 35MHz 14-pin SO-14D) tA161 PDF

    IC 7486

    Abstract: CI 74LS08 TTL 7408 IC TTL 7432 7408 TTL TTL 74ls08 7408 ic diagram IC TTL 7402 IC 7432 74LS32 TTL
    Text: FA IR C H ILD D IG ITA L TTL High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram'2’ S U. High Speed 54H/74H 6 ns/22 mW c B £ Std. TTL 54/74 10 ns/10 mW o o 54/7402 — 54S/74S02 D10 — — — — D11 4L,6B 54LS /74LS 27 54/7427 — — D12


    OCR Scan     		ns/10 54LS/74LS 54H/74H ns/22 54S/74S ns/19 54LS/74LS02 54S/74S02 54LS/74LS27 IC 7486 CI 74LS08 TTL 7408 IC TTL 7432 7408 TTL TTL 74ls08 7408 ic diagram IC TTL 7402 IC 7432 74LS32 TTL PDF

    74ls gate symbols

    Abstract: 74LS series logic gate symbols 74LS series logic gates 74LS logic gates oc 44 74LS TTL series 74LS D-32 buffer 74ls series logic gates 74LS AND GATE
    Text: FAIRCHILD DIGITAL T T L Std. TTL 9N 54/74 10 ns/10 mW High Speed 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram<2 Item ~c g o c 3 li. Low Power Schottky 54LS/74LS 5 ns/2 mW Cont’d) 9000 Series 8 ns/10 mW SSI FUNCTIONS


    OCR Scan     		ns/10 54H/74H ns/22 54S/74S ns/19 54LS/74LS 74LS266 /74LS 74ls gate symbols 74LS series logic gate symbols 74LS series logic gates 74LS logic gates oc 44 74LS TTL series 74LS D-32 buffer 74ls series logic gates 74LS AND GATE PDF

    74LS

    Abstract: CD4015B CD4015BC CD4015BM J16A
    Text: June 1996 CD4015BM/CD4015BC Dual 4-Bit Static Shift Register Features • W ide supply voltage range ■ High noise im m unity ■ Low pow e r TTL com patibility 3.0V to 18V 0.45 V DD typ. Fan o ut o f 2 driving 74L o r 1 driving 74LS ■ M edium speed operation


    OCR Scan     		CD4015BM/CD4015BC 74LS CD4015B CD4015BC CD4015BM J16A PDF

    TTL 74126

    Abstract: 74ls gate symbols 7450 ttl 74LS series logic gates 3 input or gate 74LS55 Fairchild logic/connection diagrams ttl 74LS126 74LS125 74LS367 74126 high speed
    Text: FAIRCHILD DIGITAL TT L High Speed Schottky 54S/74S 3 ns/19 mW Logic/C onnection D iagram 2 High Speed 54H/74H 6 ns/22 mW Std. TTL 9N 54/74 10 ns/10 mW 54LS/74LS 5 ns/2 mW Item ~g c su c U3_ Low Power S chottky (C o n t'd ) 9000 Series 8 ns/10 mW SSI FUNCTIONS


    OCR Scan     		ns/10 54LS/74LS 54H/74H ns/22 54S/74S ns/19 74LS266 54H/74H52 54H/74H50 TTL 74126 74ls gate symbols 7450 ttl 74LS series logic gates 3 input or gate 74LS55 Fairchild logic/connection diagrams ttl 74LS126 74LS125 74LS367 74126 high speed PDF

    Untitled

    Abstract: No abstract text available
    Text: CD4014BM CD4014BC 8-Stage Static Shift Register General Description Dual-In-Line Package Features Y Y Y Y Y Y Wide supply voltage range 3 0V to 15V High noise immunity 0 45 VDD typ Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS 5V – 10V – 15V parametric ratings


    Original     		CD4014BM CD4014BC PDF

    74LS

    Abstract: CD4015BC CD4015BM 18VQC
    Text: CD4015BM/CD4015BC i/W \ National m!m Semiconductor CD4015BM/CD4015BC DUAL 4-BIT Static Shift Register General Description fan ou t o f 2 d rivin g 74L or 1 driving 74LS Low pow er TTL c o m p a tib ility The CD4015BM/CD4015BC c o n ta in s tw o id e n tic a l,


    OCR Scan     		CD4015BM/CD4015BC 74LS CD4015BC CD4015BM 18VQC PDF

    MM74HC138M

    Abstract: 74HC 74LS138 M16A M16D MM74HC138 MM74HC138MTC MM74HC138SJ MTC16 mm74hc138n
    Text: s e m i c o n d u c t o r Revised February 1999 MM74HC138 3-to-8 Line Decoder General Description The d ecoder’s outputs can drive 10 low pow er S chottky TTL equivalent loads, and are functionally and pin equiva­ lent to the 74LS 138. All inputs are protected from dam age


    OCR Scan     		MM74HC138 MM74HC138M 74HC 74LS138 M16A M16D MM74HC138MTC MM74HC138SJ MTC16 mm74hc138n PDF

    Untitled

    Abstract: No abstract text available
    Text: October 1987 Revised January 1999 S E M ¡ C O N D U C T O R TM Features • Wide supply voltage range: ■ High noise immunity: 3.0V to 15V 0.45 Vqq typ. ■ Low power TTL compatibility: or 1 driving 74LS ■ New formula: C in Farads) PW 0 ut = RC Fan out of 2 driving 74L


    OCR Scan     		CD4528BC CD4538BCM 16-Lead CD4538BC PDF