F74B
Abstract: No abstract text available
Text: SPEED/PACKAGE AVAILABILITY 54 f ;w 54H F,W 54LS F,W 54S F,W 74 74H 74LS 74S PIN CONFIGURATION A,F A,F A,F A,F 74.74H, 54/74LS, 54/748 A,F,W PACKAGE SWITCHING CHARACTERISTICS TEST CONDITIONS PARAMETER 54,54« W PACKAGE v C C - 5V, TA = 25°C 54/74 54/74H 54/74LS
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54/74LS,
133fi
54/74H
54/74LS
667Si
54/74S
F74B
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74LS
Abstract: 400fi
Text: SPEED/PACKAG E AVAILABILITY PIN CONFIGURATION 74 A,F 74H A,F 74LS A,F 54 F,W 54H F,W 54LS F,W 74, 74H, 54/74LS A,F,W PA CK A G E SWITCHING CHARACTERISTICS T EST CON DITIO NS PARAM ETER MIN V C C - 5V, TA = 25°C 54/74 54/74H 54/74LS C|.=15pF RL = 40012 C L =25pF
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54/74LS
54/74H
280S2
400fi
74LS
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Untitled
Abstract: No abstract text available
Text: M MOTOROLA. SN54/74LS90 SN54/74LS92 SN54/74LS93 DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER The SN 54/74LS 90, S N 54/74LS 92 and S N 54/74LS 93 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or
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SN54/74LS90
SN54/74LS92
SN54/74LS93
54/74LS
modulo-12,
modulo-16
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Untitled
Abstract: No abstract text available
Text: 257A INPUT LO ADING /FAN -O U T: See Section 3 for U.L. definitions PIN NAMES Zn . DESCRIPTION 3-State O utputs 54/74LS U.L. HIG H/LO W A* V ' K 65/15 (25)/(7.5) DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (uni ess otherwise specified) SYMBOL 54/74LS
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54/74LS
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LS623
Abstract: D2537 SN74LS620
Text: S N 54LS 620, SN 54LS621, SN 74LS 620, SN 74LS 621, SM 74LS623 OCTAL BUS TRANSCEIVERS D2537, AUGUST 1979-REVISEO MARCH 1988 SN 54LS620, S N 54LS621, S N & 4 L S 6 2 2 . . . J P AC K A G E S N 74LS 620, S N 74LS621, S N 7 4 L S 6 2 3 . . . D W O R N P AC K A G E
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54LS621,
74LS623
D2537,
1979-REVISEO
20-Pin
54LS620,
74LS621,
LS623
D2537
SN74LS620
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Untitled
Abstract: No abstract text available
Text: AVG DDi Semiconductors Technical Data 192, 193 Synchronous Up/Down Decade and Binary Counters with CLEAR DV74LS192 DV74ALS192 DV74LS193 DV74ALS193 The 74LS/ALS192 is an UP/DOWN BCD Decade 8421 Counter and the 74LS/ALS193 is an UP/DOWN MODULO-16 Binary
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DV74LS192
DV74ALS192
DV74LS193
DV74ALS193
74LS/ALS192
74LS/ALS193
MODULO-16
ALS192
LS192
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MAX2754
Abstract: No abstract text available
Text: SPEED/PACKAG E AVAILABILITY 54 54H 54LS 54S F,W F,W F,W F,W 74 74H 74LS 74S PIN CONFIGURATION A,F A,F A,F A,F vcc= 5V, t a = 25 °c SWITCHING CHARACTERISTICS TEST CONDITIONS PARAMETER 54/74 54/74H 54/74LS 54/74S C|.=15pF RL =400fl CL =25pF RL=280Q CL =15pF
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54/74H
54/74LS
54/74S
280Si
400fl
MAX2754
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Untitled
Abstract: No abstract text available
Text: AVG DDi Semiconductors Technical Data DV74LS190 DV74ALS190 DV74LS191 DV74ALS191 Synchronous Up/Down Decade and Binary Counters The 74LS/ALS 190 is a synchronous UP/DOWN BCD Decade counter 8421 The 74LS/ALS 191 is a synchronous UP/DOWN Modulo-16 Binary Counter. State changes of the counters are
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DV74LS190
DV74ALS190
DV74LS191
DV74ALS191
74LS/ALS
Modulo-16
ALS190
LS190
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IC 74LS14
Abstract: 74ls14 74LSxx ic 74ls13
Text: M OTOROLA SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The S N 54LS /74LS 13 and SN 54LS /74LS 14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into
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/74LS
SN54/74LS13
SN54/74LS14
IC 74LS14
74ls14
74LSxx
ic 74ls13
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54LS244
Abstract: No abstract text available
Text: LS244 National Semiconductor 54LS244/DM74LS244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers General Description • Typical Iq i_ sink current 54LS 12 mA 74LS 24 mA ■ Typical Ioh (source current) 54LS - 1 2 mA 74LS - 1 5 mA ■ Typical propagation delay times
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54LS244/DM74LS244
667il
667ii
667fi
667fl
667ii
54LS244
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LS748
Abstract: 74LS147 74LS148 74lS748
Text: g MOTOROLA SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The S N 54/74LS 147 and the SN 54/74LS 148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order
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10-LINE-TO-4-LINE
54/74LS
LS147
LS148
SN54/74LS148
SN54/74LS748
LS148)
LS748)
LS748
74LS147
74LS148
74lS748
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74LS
Abstract: I50F 74LSc
Text: SPEED/PACKAGE AVAILABILITY 54 F,W 54LS F,W PIN CONFIGURATION 74 A,F 74LS A,F A,F,W PACKAGE SWITCHING CHARACTERISTICS T E S T CONDITIONS PARAMETER VCc = 5V, TA = 25°C 54/74 54/74LS C L =50pF RL =133i! C|_=45pF RL=667iî MIN TYP MAX 10 15 MIN TYP MAX UNIT 20
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54/74LS
133ff
54/74S
74LS
I50F
74LSc
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74LS24
Abstract: DM54LS244J DM74LS244WM 54LS 74LS DM74LS244N J20A DM54LS244
Text: DM54LS244/DM74LS244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers General Description • Typical Io l sink current 54LS 12 mA 74LS 24 mA ■ Typical Ioh (source current) 54LS - 1 2 mA 74LS - 1 5 mA ■ Typical propagation delay times Inverting 10.5 ns
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DM54LS244/DM74LS244
133ii.
74LS24
DM54LS244J
DM74LS244WM
54LS
74LS
DM74LS244N
J20A
DM54LS244
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74LS14 not gate
Abstract: 74LS14 74ls14 ttl ttl 74ls14 74LS14 DATA LS14 74LS13 TTL Schmitt-Trigger Inverters 751A-02 LS13
Text: MOTOROLA SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The SN 54LS /74LS 13 and S N 54LS /74LS 14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into
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SN54LS/74LS13
SN54LS/74LS14
SN54/74LS13
SN54/74LS14
74LS14 not gate
74LS14
74ls14 ttl
ttl 74ls14
74LS14 DATA
LS14
74LS13
TTL Schmitt-Trigger Inverters
751A-02
LS13
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4QFC
Abstract: S62D
Text: SN54LS595, SN54LS596, SN74LS595, SN74LS596 8 BIT SH IFT REGISTERS W ITH O U TPU T LATC H ES 02634, JANUARY 1981 - REVISED MARCH 1988 S N 54LS 595, SN64LS596 . . . J OR W PACKAGE SN 74LS 595, S N 74LS 596 . . . N PACKAGE 8-Bit Serial-ln, Parallel-Out Shift
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SN54LS595,
SN54LS596,
SN74LS595,
SN74LS596
XS596)
SN64LS596
LS595
LS596
4QFC
S62D
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Untitled
Abstract: No abstract text available
Text: MOTOROLA SN54/74LS168 SN54/74LS169 BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS The SN 54/74LS 168 and SN 54/74LS 169 are fully synchronous 4-stage up/down counters featuring a preset capability for programmable operation, carry lookahead for easy cascading and a U /D input to control the direction
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54/74LS
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74LS147
Abstract: 74LS148 74ls748 LS748 PIN 74LS147 LS148 ttl 74ls147 LS 74LS147 6200S ttl 74ls148
Text: <8 > MOTOROLA SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The S N 54/74LS 147 and the S N 54/74LS 148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order
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10-LINE-TO-4-LINE
54/74LS
LS147
LS148
SN54/74LS148
SN54/74LS748
LS148)
LS748)
74LS147
74LS148
74ls748
LS748
PIN 74LS147
ttl 74ls147
LS 74LS147
6200S
ttl 74ls148
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ls190
Abstract: 30132 10116
Text: 190,191 AVG Semiconductors DDT Technical Data DV74LS190 DV74ALS190 DV74LS191 DV74ALS191 Synchronous Up/Down Decade and Binary Counters The 74LS/ALS 190 is a synchronous UP/DOWN BCD Decade counter 8421 The 74LS/ALS 191 is a synchronous UP/DOWN Modulo-16 Binary Counter. State changes of the counters are
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74LS/ALS
Modulo-16
varieS190-191
LS190
Ci-15pF
ALS190
DV74LS190-191,
DV74ALS190-191
30132
10116
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74ls characteristics
Abstract: 74LS 74LS AND propagation delay
Text: SPEED /PACK AG E AVAILABILITY PIN CONFIGURATION 74H A ,F 74LS A ,F 74S A,F 54H F,W 54LS F,W S4S F,W 74H,54/74LS,54/74S A,F,W PACK AG E Positive logic: Y-*A8CD NC-No internal connection SWITCHING CHARACTERISTICS v C C - 5V, T A = 25 »c T E S T CONDITIONS PARAMETER
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54/74LS
54/74S
54/74H
-15pF
280i2
74ls characteristics
74LS
74LS AND propagation delay
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Untitled
Abstract: No abstract text available
Text: SPEED/PACKAGE AVAILABILITY 54 F.W 54LS F.W 54S F,W 74 A,F 74LS A,F 74S A,F SWITCHING CHARACTERISTICS vcc TEST CONDITIO NS PARAM ETER = 5V, t a = 25 »c 54/74 54/74LS 54/748 C L =45pF RL=133fl C L =45pF R L =667iî CL=15pF R|_=93!2 MIN TYP MAX 14 22 MIN TYP
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54/74LS
133fl
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20-PIN
Abstract: M74LS37P
Text: MITSUBISHI LSTTLs M 74LS 37P Q U A D RU PLE 2-IN P U T P O S IT IV E NAND B U FFER DESCRIPTION The M 74LS 37P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing four 2-in p u t positive N A N D and negative NOR buffer gates. FEATURES
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M74LS37P
M74LS37P
b2LHfl27
0013Sbl
14-PIN
16-PIN
20-PIN
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74LS299 APPLICATIONS
Abstract: No abstract text available
Text: M MOTOROLA SN54/74LS323 8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS The S N 54/74LS 323 is an 8-Bit Universal S hift/S torage Register with 3-state outputs. Its function is sim ilarto the SN 54/74LS 299 with the exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are
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SN54/74LS323
54/74LS
SN54/74LS323
74LS299 APPLICATIONS
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Untitled
Abstract: No abstract text available
Text: M MOTOROLA SN54/74LS490 DUAL DECADE COUNTER The S N 54/74LS 490 contains a pair of high-speed 4-stage ripple counters. Each half of the S N 54/74LS 490 has individual Clock, Master Reset and Mas ter Set (Preset 9) inputs. Each section counts in the 8, 4, 2, 1 BCD code.
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SN54/74LS490
54/74LS
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74LS74
Abstract: No abstract text available
Text: SPEED/PACKAG E AVAILABILITY 54 F 54LS F,W 54S F,W 74 74LS 74S PIN CONFIGURATION A,F A,F A,F A,F,W PA C K A G E SWITCHING CHARACTERISTICS vCc TEST CON DITIO NS PARAM ETER = 5V, t a - 25 °c 54/74 54/74LS 54/74S C L =15pF RL =400H C L =15pF R|_=2KS C|_=15pF
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54/74LS
54/74S
280S2
54/74H
-280S2
-15pF
400fl
74LS74
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