IC 74LS14
Abstract: 74ls14 74LSxx ic 74ls13
Text: M OTOROLA SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The S N 54LS /74LS 13 and SN 54LS /74LS 14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into
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/74LS
SN54/74LS13
SN54/74LS14
IC 74LS14
74ls14
74LSxx
ic 74ls13
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74LS14 not gate
Abstract: 74LS14 74ls14 ttl ttl 74ls14 74LS14 DATA LS14 74LS13 TTL Schmitt-Trigger Inverters 751A-02 LS13
Text: MOTOROLA SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The SN 54LS /74LS 13 and S N 54LS /74LS 14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into
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SN54LS/74LS13
SN54LS/74LS14
SN54/74LS13
SN54/74LS14
74LS14 not gate
74LS14
74ls14 ttl
ttl 74ls14
74LS14 DATA
LS14
74LS13
TTL Schmitt-Trigger Inverters
751A-02
LS13
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Untitled
Abstract: No abstract text available
Text: M MOTOROLA. SN54/74LS90 SN54/74LS92 SN54/74LS93 DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER The SN 54/74LS 90, S N 54/74LS 92 and S N 54/74LS 93 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or
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SN54/74LS90
SN54/74LS92
SN54/74LS93
54/74LS
modulo-12,
modulo-16
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Untitled
Abstract: No abstract text available
Text: AVG DDi Semiconductors Technical Data 192, 193 Synchronous Up/Down Decade and Binary Counters with CLEAR DV74LS192 DV74ALS192 DV74LS193 DV74ALS193 The 74LS/ALS192 is an UP/DOWN BCD Decade 8421 Counter and the 74LS/ALS193 is an UP/DOWN MODULO-16 Binary
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DV74LS192
DV74ALS192
DV74LS193
DV74ALS193
74LS/ALS192
74LS/ALS193
MODULO-16
ALS192
LS192
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74ls48 PIN OUT
Abstract: No abstract text available
Text: <8> M OTOROLA D E S C R IP T IO N — The S N 54LS /74LS 48 and S N 54LS /74LS 49 are BCD to 7-Segm ent Decoders consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. The LS49 offers active HIGH opencollector outputs for current-sourcing applications to drive logic circuits
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/74LS
74ls48 PIN OUT
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LS155
Abstract: 74ls155 74 ls 155 demultiplexer 74ls156
Text: MOTOROLA SN54/74LS155 SN54/74LS156 DUAL 1-0F-4 DECODER/ DEMULTIPLEXER The SN 54/74LS 155 and S N 54/74LS 156 are high speed Dual 1-of-4 Decoder/Demultiplexers. These devices have two decoders with common 2-bit Address inputs and separate gated Enable inputs. Decoder “a” has an
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54/74LS
LS156
LS155
74ls155
74 ls 155 demultiplexer
74ls156
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74ALS192
Abstract: IC 74LS192 LS192 ALS192 MODULO-16 DV74LS192 DV74LS192-93 LS193
Text: AVG Semiconductors DDT Technical Data The 74LS/ALS192 is an UP/DOWN BCD Decade 8421 Counter and the 74LS/ALS193 is an UP/DOWN MODULO-16 Binary Counter. Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously. The out
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74LS192
74ALS192
74LS/ALS193
MODULO-16
clock92-93,
DV74ALS192-93
1-800-AVG-SEMI
LS192,
ALS192,
LS192
IC 74LS192
ALS192
DV74LS192
DV74LS192-93
LS193
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74LS90 pin configuration
Abstract: configuration 74ls90
Text: SPEED/PACKAGE AVAILABILITY 54 F,W S4LS F,W BLOCK DIAGRAM 54LS/74LS PIN CONFIGURATION 74 A,F 74LS A,F DESCRIPTION This monolithic counter contains four mas ter-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the
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54LS/74LS
54/74LS90
74LS90 pin configuration
configuration 74ls90
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20-PIN
Abstract: M74LS37P
Text: MITSUBISHI LSTTLs M 74LS 37P Q U A D RU PLE 2-IN P U T P O S IT IV E NAND B U FFER DESCRIPTION The M 74LS 37P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing four 2-in p u t positive N A N D and negative NOR buffer gates. FEATURES
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M74LS37P
M74LS37P
b2LHfl27
0013Sbl
14-PIN
16-PIN
20-PIN
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Untitled
Abstract: No abstract text available
Text: AVG DDi Semiconductors Technical Data DV74LS190 DV74ALS190 DV74LS191 DV74ALS191 Synchronous Up/Down Decade and Binary Counters The 74LS/ALS 190 is a synchronous UP/DOWN BCD Decade counter 8421 The 74LS/ALS 191 is a synchronous UP/DOWN Modulo-16 Binary Counter. State changes of the counters are
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DV74LS190
DV74ALS190
DV74LS191
DV74ALS191
74LS/ALS
Modulo-16
ALS190
LS190
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74LS18P
Abstract: No abstract text available
Text: MITSUBISHI LSTTLs M 74LS 18P DUAL 4-IN P U T NAND SCHMITT TRIGGER DESCRIPTION The M 74LS 18P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing tw o 4-input positive-logic N A N D gates having a schm itt trigger function and negative-logic N O R gates.
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500ns,
b2LHfl27
0013Sbl
74LS18P
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74ls290
Abstract: IC 74ls290
Text: MOTOROLA SN54/74LS290 SN54/74LS293 DECADE COUNTER; 4-BIT BINARY COUNTER The SN 54/74LS 290 and S N 54/74LS 293 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two sec tion and either a divide-by-five LS290 or divide-by-eight (LS293) section
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SN54/74LS290
SN54/74LS293
54/74LS
LS290)
LS293)
odulo-16
LS290
74ls290
IC 74ls290
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ls190
Abstract: 30132 10116
Text: 190,191 AVG Semiconductors DDT Technical Data DV74LS190 DV74ALS190 DV74LS191 DV74ALS191 Synchronous Up/Down Decade and Binary Counters The 74LS/ALS 190 is a synchronous UP/DOWN BCD Decade counter 8421 The 74LS/ALS 191 is a synchronous UP/DOWN Modulo-16 Binary Counter. State changes of the counters are
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74LS/ALS
Modulo-16
varieS190-191
LS190
Ci-15pF
ALS190
DV74LS190-191,
DV74ALS190-191
30132
10116
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Untitled
Abstract: No abstract text available
Text: g MOTOROLA SN54/74LS290 SN54/74LS293 DECADE COUNTER; 4-BIT BINARY COUNTER The S N 54/74LS 290 and S N 54/74LS 293 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two sec tion and either a divide-by-five (LS290) or divide-by-eight (LS293) section
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SN54/74LS290
SN54/74LS293
54/74LS
LS290)
LS293)
odulo-16
LS290
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74ls51p
Abstract: No abstract text available
Text: MITSUBISHI LSTTLs M 74LS 51P DUAL 2 -W ID E 2 -IN P U T /3 -IN P U T AND -O R -IN VER T GATE DESCRIPTION The M 74LS 51P is a semiconductor integrated PIN CONFIGURATION TOP VIEW circuit containing dual 2-wide 2-in p u t/3 -in p u t A N D -O R -IN V E R T
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500ns,
0013Sbl
14-PIN
16-PIN
20-PIN
74ls51p
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74HCTLS
Abstract: No abstract text available
Text: h ftr e ZX54HCTLS ZX74HCTLS x § # ZX54HCTLS ZX74HCTLS Dual AND-OR-Invert Gates and Dual AND-OR Gates February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family The '51 performs the following Boolean functions:
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54/74LS
74HCTLS:
54HCTLS:
ZX54HCTLS
ZX74HCTLS
74HCTLS
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HCTLS
Abstract: 74hctls
Text: Z v t n ZX54HCTLS M ZX74HCTLS x February 1985 Quad 2-Input AND Gates with Open-Drain Outputs OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-Input AND
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ZX54HCTLS
ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
HCTLS
74hctls
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HCTLS266
Abstract: 74HCTLS
Text: Zvtrex ZX54HCTLS ZX74HCTLS 266 Quad Exdusive-NOR Gates with Open-Drain Outputs February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent exclusive-NOR
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ZX54HCTLS
ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
HCTLS266
74HCTLS
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74hctls
Abstract: No abstract text available
Text: Zytrex_ sags12 Triple 3-Input NAND Gates with Open-Drain Outputs February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin*out, speed and drive compatibility with 54/74LS logic family These devices contain three independent 3-input NAND
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ZX54HCTLS
ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
74hctls
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M74LS09P
Abstract: 20-PIN
Text: MITSUBISHI LSTTLs M74LS09P QUADRUPLE 2-IN P U T POSITIVE AND GATES W ITH OPEN COLLECTOR OUTPUTS DESCRIPTION The M 74LS 09P is a semiconductor integrated circuit containing 4 dual-input positive A N D and negative OR gates w ith open collector output. FEATURES
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M74LS09P
M74LS09P
16-PIN
20-PIN
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74HCTLS
Abstract: No abstract text available
Text: Zytrex ZXS4HCTLS ZX74HCTLS February 1985 11 Triple 3-Input AND Gates O BJECTIVE S P E C IF IC A TIO N S Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain three independent 3-input AND
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54/74LS
74HCTLS:
54HCTLS:
ZX54HCTLS
ZX74HCTLS
74HCTLS
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Altera EP1800
Abstract: EP1800 JEDEC FORMAT EP1800 altera logicaps TTL library SCHEMA PA BUILT UP EP1800 LOGIC DIAGRAM ep18001
Text: EP1800 Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conventional and custom logic. Speed equivalent to 74LS TTL with 25 MHz clock rates. “Zero Power” typically 10/jA standby . Active power of 250 mW at 5 MHz.
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EP1800
Altera EP1800
EP1800 JEDEC FORMAT
EP1800
altera logicaps TTL library
SCHEMA PA BUILT UP
EP1800 LOGIC DIAGRAM
ep18001
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Zytrex quad and gate
Abstract: 74hctls
Text: Z y tr c x _ February1985 08 Quad 2-Input AND Gâté# / OBJECTIVE SPECIFICATIONS Features Description • Function, pln-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-input AND gates. They perform the Boolean functions Y = A • B or
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ZX54HCTLS
ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
Zytrex quad and gate
74hctls
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Zytrex OR gate
Abstract: 74HCTLS
Text: Z v t r e ZX54HCTLS ZX74HCTLS x Quad 2-Input Exclusive-OR Gates February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-input Exclu
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54/74LS
74HCTLS:
54HCTLS:
ZX54HCTLS
ZX74HCTLS
Zytrex OR gate
74HCTLS
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