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    74H101FC Search Results

    74H101FC Datasheets (1)

    Part ECAD Model Manufacturer Description Curated Type PDF
    74H101FC Fairchild Semiconductor JK Edge Triggered Flip-Flop Scan PDF

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    74H101

    Abstract: No abstract text available
    Text: n a t i o n a l s e n I c o n d -clogio 0 2 e d I b s o n a B Got377s 3 I T -^ 6 -0 7 '0 7 101 CO N N ECTIO N DIAGRAM S PINO UT A 54H/74H101 JK EDGE-TRIGGERED FLIP-FLOP (with A N D - O R Inputs D ESC R IP TIO N — The '101 is a high speed J K negative edge-triggered flipflop. The AND-OR gate inputs are inhibited while the clock input is LOW.


    OCR Scan     		PDF Got377s 54H/74H101 54/74H 74H101

    IC LA 4138

    Abstract: No abstract text available
    Text: 101 CONNECTION DIAGRAMS P IN O U T A 54H/74H101 0 JK EDGE-TRIGGERED FLIP-FLOP with A N D -O R Inputs DESCRIPTION — The '101 is a high speed J K negative edge-triggered flipflop. The A N D -O R gate inputs are inhibited w hile the clo ck input is LOW. When the clo ck goes HIGH, the inputs are enabled and data will be accepted.


    OCR Scan     		PDF 54H/74H101 54/74H IC LA 4138

    74H101

    Abstract: 54H101 54H101FM 74H101DC 74H101FC 74H101PC 74hcl
    Text: 101 CO N N ECTIO N DIAGRAMS P IN O U T A 54H/74H101 0 JK EDGE-TRIGGERED FLIP-FLOP with AND-OR Inputs D E S C R IP T IO N — The '101 is a high speed J K negative edge-triggered flip­ flop. T he A N D-O R gate inputs are inhibited while the clock input is LOW.


    OCR Scan     		PDF 54H/74H101 54/74H 74H101 54H101 54H101FM 74H101DC 74H101FC 74H101PC 74hcl