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    74AUP2G79GM Search Results

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    74AUP2G79GM Price and Stock

    Rochester Electronics LLC 74AUP2G79GM,125

    IC FF D-TYPE DUAL 1BIT 8XQFN
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    DigiKey 74AUP2G79GM,125 Bulk 24,491 1,776
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    74AUP2G79GM,125 Bulk 1,776
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    Nexperia 74AUP2G79GM,125

    IC FF D-TYPE DUAL 1BIT 8XQFN
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    DigiKey 74AUP2G79GM,125 Reel
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    Avnet Americas 74AUP2G79GM,125 Reel 4,000
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    Rochester Electronics 74AUP2G79GM,125 74,276 1
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    NXP Semiconductors 74AUP2G79GM,125

    74AUP2G79GM - D Flip-Flop, AUP/ULP/V Series, 2-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PQCC8 '
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    Rochester Electronics 74AUP2G79GM,125 24,491 1
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    74AUP2G79GM Datasheets (5)

    Part ECAD Model Manufacturer Description Curated Type PDF
    74AUP2G79GM NXP Semiconductors Low-power dual D-type flip-flop; positive-edge trigger Original PDF
    74AUP2G79GM NXP Semiconductors Low-power dual D-type flip-flop, positive-edge trigger Original PDF
    74AUP2G79GM NXP Semiconductors 74AUP2G79 - IC AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC8, 1.60 X 1.60 MM, 0.50 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MO-255, SOT902-2, QFN-8, FF/Latch Original PDF
    74AUP2G79GM,125 NXP Semiconductors Low-power dual D-type flip-flop; positive-edge trigger; Package: SOT902-1 (XQFN8U); Container: Reel Pack, Reverse, Reverse Original PDF
    74AUP2G79GM,125 NXP Semiconductors 74AUP2G79 - IC AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC8, 1.60 X 1.60 MM, 0.50 MM HEIGHT, PLASTIC, MO-255, SOT-902-1, XQFN-8, FF/Latch Original PDF

    74AUP2G79GM Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Dual D-type flip-flop positive-edge trigger

    Abstract: No abstract text available
    Text: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 6 — 8 December 2011 Product data sheet 1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input nD is transferred to the nQ output on the LOW-to-HIGH transition of the


    Original     		PDF 74AUP2G79 74AUP2G79 Dual D-type flip-flop positive-edge trigger

    Dual D-type flip-flop positive-edge trigger

    Abstract: JESD22-A114E JESD78 74AUP2G79 74AUP2G79DC 74AUP2G79GT p79 marking
    Text: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 04 — 30 June 2009 Product data sheet 1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input nD is transferred to the nQ output on the LOW-to-HIGH transition of the


    Original     		PDF 74AUP2G79 74AUP2G79 Dual D-type flip-flop positive-edge trigger JESD22-A114E JESD78 74AUP2G79DC 74AUP2G79GT p79 marking

    74AUP2G79

    Abstract: 74AUP2G79DC 74AUP2G79GM 74AUP2G79GT JESD22-A114E JESD78
    Text: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 02 — 19 March 2008 Product data sheet 1. General description The 74AUP2G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.


    Original     		PDF 74AUP2G79 74AUP2G79 74AUP2G79DC 74AUP2G79GM 74AUP2G79GT JESD22-A114E JESD78

    Untitled

    Abstract: No abstract text available
    Text: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 8 — 24 January 2013 Product data sheet 1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input nD is transferred to the nQ output on the LOW-to-HIGH transition of the


    Original     		PDF 74AUP2G79 74AUP2G79

    74AUP2G79

    Abstract: 74AUP2G79DC 74AUP2G79GT JESD78
    Text: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 5 — 30 September 2010 Product data sheet 1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input nD is transferred to the nQ output on the LOW-to-HIGH transition of the


    Original     		PDF 74AUP2G79 74AUP2G79 74AUP2G79DC 74AUP2G79GT JESD78

    74AUP2G79

    Abstract: 74AUP2G79DC 74AUP2G79GM 74AUP2G79GT SN74AUC2G79 SN74AUC2G79DCTR
    Text: SLG74LB2G79 GreenLIBTM DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP General Description Features The GreenLIB provides a low-power, low-voltage dual • Pb-Free / RoHS Compliant positive-edge-triggered D-type flip-flop. When data at the • Halogen-Free data D input meets the setup time requirement, the data is


    Original     		PDF SLG74LB2G79 LB2G79 000-0074LB2G79-11 74AUP2G79 74AUP2G79DC 74AUP2G79GM 74AUP2G79GT SN74AUC2G79 SN74AUC2G79DCTR

    Untitled

    Abstract: No abstract text available
    Text: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 01 — 6 October 2006 Product data sheet 1. General description The 74AUP2G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.


    Original     		PDF 74AUP2G79 74AUP2G79

    74AUP2G79

    Abstract: 74AUP2G79DC 74AUP2G79GT JESD22-A114E JESD78
    Text: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 03 — 1 April 2009 Product data sheet 1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input nD is transferred to the nQ output on the LOW-to-HIGH transition of the


    Original     		PDF 74AUP2G79 74AUP2G79 74AUP2G79DC 74AUP2G79GT JESD22-A114E JESD78

    Untitled

    Abstract: No abstract text available
    Text: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 7 — 14 June 2012 Product data sheet 1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input nD is transferred to the nQ output on the LOW-to-HIGH transition of the


    Original     		PDF 74AUP2G79 74AUP2G79