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    74AUP1 Search Results

    74AUP1 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74AUP1G125DCKRG4 Texas Instruments Low-Power Single Bus Buffer Gate with 3-State Output 5-SC70 -40 to 85 Visit Texas Instruments Buy
    SN74AUP1G02DBVR Texas Instruments Low-Power Single 2-Input Positive-NOR Gate 5-SOT-23 -40 to 85 Visit Texas Instruments Buy
    SN74AUP1G04DCKR Texas Instruments Low-Power Single Inverter Gate 5-SC70 -40 to 85 Visit Texas Instruments Buy
    SN74AUP1G06DBVRG4 Texas Instruments Low-Power Single Inverter Buffer/Driver with Open-Drain Outputs 5-SOT-23 -40 to 85 Visit Texas Instruments Buy
    SN74AUP1G06DRLR Texas Instruments Low-Power Single Inverter Buffer/Driver with Open-Drain Outputs 5-SOT-5X3 -40 to 85 Visit Texas Instruments Buy
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    74AUP1 Price and Stock

    Nexperia 74AUP1T14GWH

    IC INVERT SCHMITT 1CH 1IN 5TSSOP
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    DigiKey 74AUP1T14GWH Reel 30,000 3,000
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    Mouser Electronics 74AUP1T14GWH 26,410
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    Chip1Stop 74AUP1T14GWH Cut Tape 3,000
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    Texas Instruments SN74AUP1G97DCKR

    IC CONFIG MULT-FUNC GATE SC70-6
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    DigiKey SN74AUP1G97DCKR Reel 15,000 3,000
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    Bristol Electronics SN74AUP1G97DCKR 2,020
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    Rochester Electronics SN74AUP1G97DCKR 2,851 1
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    Win Source Electronics SN74AUP1G97DCKR 112,000
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    Texas Instruments SN74AUP1T50DCKR

    IC BUF NON-INVERT 3.6V SC70-5
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    DigiKey SN74AUP1T50DCKR Reel 9,000 3,000
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    Chip1Stop SN74AUP1T50DCKR Cut Tape 2,694
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    Win Source Electronics SN74AUP1T50DCKR 6,000
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    Diodes Incorporated 74AUP1G00FZ4-7

    IC GATE NAND 1CH 2-INP DFN1410-6
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    DigiKey 74AUP1G00FZ4-7 Reel 5,000 5,000
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    74AUP1G00FZ4-7 Cut Tape 4,000 1
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    Diodes Incorporated 74AUP1G02FS3-7

    IC GATE NOR 1CH 2-INP DFN0808-4
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    DigiKey 74AUP1G02FS3-7 Cut Tape 5,000 1
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    74AUP1G02FS3-7 Digi-Reel 5,000 1
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    74AUP1G02FS3-7 Reel 5,000 5,000
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    Avnet Silica 74AUP1G02FS3-7 5,000 10 Weeks 5,000
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    74AUP1 Datasheets (500)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74AUP1G00 Diodes SINGLE 2 INPUT POSITIVE NAND GATE Original PDF
    74AUP1G00 NXP Semiconductors Advanced ultra-low-power CMOS logic; NXP ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx Original PDF
    74AUP1G00 Philips Semiconductors Low-power 2-input NAND gate Original PDF
    74AUP1G00FS3-7 Diodes Integrated Circuits (ICs) - Logic - Gates and Inverters - IC GATE NAND 1CH 2-INP DFN0808-4 Original PDF
    74AUP1G00FW4-7 Diodes SINGLE 2 INPUT POSITIVE NAND GATE Original PDF
    74AUP1G00FW5-7 Diodes Integrated Circuits (ICs) - Logic - Gates and Inverters - IC GATE NAND 1CH 2-INP DFN1010-6 Original PDF
    74AUP1G00FZ4-7 Diodes SINGLE 2 INPUT POSITIVE NAND GATE Original PDF
    74AUP1G00GF NXP Semiconductors Low-power 2-input NAND gate Original PDF
    74AUP1G00GF Philips Semiconductors Low-power 2-input NAND gate Original PDF
    74AUP1G00GF,132 NXP Semiconductors 74AUP1G00 - IC AUP/ULP/V SERIES, 2-INPUT NAND GATE, PDSO6, 1 X 1 MM, 0.50 MM HEIGHT, PLASTIC, SOT-891, SON-6, Gate Original PDF
    74AUP1G00GM NXP Semiconductors Low-power 2-input NAND gate Original PDF
    74AUP1G00GM Philips Semiconductors Low-power 2-input NAND gate Original PDF
    74AUP1G00GM,115 NXP Semiconductors 74AUP1G00 - IC AUP/ULP/V SERIES, 2-INPUT NAND GATE, PDSO6, 1 X 1.45 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-886, SON-6, Gate Original PDF
    74AUP1G00GM,115 NXP Semiconductors Low-power 2-input NAND gate; Package: SOT886 (XSON6); Container: Tape reel smd Original PDF
    74AUP1G00GM,125 NXP Semiconductors 74AUP1G00GM - Low-power 2-input NAND gate, SOT886 Package, Standard Marking, Reel Pack, Reverse Original PDF
    74AUP1G00GM,132 NXP Semiconductors 74AUP1G00 - IC AUP/ULP/V SERIES, 2-INPUT NAND GATE, PDSO6, 1 X 1.45 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-886, SON-6, Gate Original PDF
    74AUP1G00GM,132 NXP Semiconductors Low-power 2-input NAND gate; Package: SOT886 (XSON6); Container: Tape reel smd Original PDF
    74AUP1G00GM-H NXP Semiconductors 74AUP1G00GM - Low-power 2-input NAND gate Original PDF
    74AUP1G00GM-H NXP Semiconductors Low-power 2-input NAND gate Original PDF
    74AUP1G00GN NXP Semiconductors Low-power 2-input NAND gate Original PDF
    ...

    74AUP1 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74AUP1G80

    Abstract: 74AUP1G80GF 74AUP1G80GM 74AUP1G80GW MO-203
    Text: 74AUP1G80 Low-power D-type flip-flop; positive-edge trigger Rev. 01 — 20 October 2006 Product data sheet 1. General description The 74AUP1G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.


    Original     		PDF 74AUP1G80 74AUP1G80 74AUP1G80GF 74AUP1G80GM 74AUP1G80GW MO-203

    74AUP1G19GM

    Abstract: 74AUP1G19GW JESD22-A114E
    Text: 74AUP1G19 Low-power 1-of-2 decoder/demultiplexer Rev. 01 — 13 August 2008 Product data sheet 1. General description The 74AUP1G19 provides a 1-of-2 decoder/demultiplexer with a common output enable. It buffers the data on input pin A and passes it either to output pin 1Y true or 2Y


    Original     		PDF 74AUP1G19 74AUP1G19 74AUP1G19GM 74AUP1G19GW JESD22-A114E

    74AUP1G126

    Abstract: 74AUP1G32 JESD22-A114E 74AUP1T1326
    Text: 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state Rev. 01 — 20 January 2009 Product data sheet 1. General description The 74AUP1T1326 is a high-performance, low-power, low-voltage, single-bit, dual supply buffer/line driver with output enable circuitry.


    Original     		PDF 74AUP1T1326 74AUP1T1326 74AUP1G32 74AUP1G126. 74AUP1G126 JESD22-A114E

    74AUP1G58

    Abstract: 74AUP1G58GF 74AUP1G58GM JESD22-A114E
    Text: 74AUP1G58 Low-power configurable multiple function gate Rev. 02 — 26 March 2009 Product data sheet 1. General description The 74AUP1G58 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,


    Original     		PDF 74AUP1G58 74AUP1G58 74AUP1G58GF 74AUP1G58GM JESD22-A114E

    74AUP1G126

    Abstract: 74AUP1G126GF 74AUP1G126GM 74AUP1G126GW JESD22-A114-C MO-203
    Text: 74AUP1G126 Low-power buffer/line driver; 3-state Rev. 02 — 28 June 2006 Product data sheet 1. General description The 74AUP1G126 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all


    Original     		PDF 74AUP1G126 74AUP1G126 74AUP 74AUP1G126GF 74AUP1G126GM 74AUP1G126GW JESD22-A114-C MO-203

    74AUP1G00GW

    Abstract: 74AUP1G00 74AUP1G00GF 74AUP1G00GM
    Text: 74AUP1G00 Low-power 2-input NAND gate Rev. 3 — 7 October 2010 Product data sheet 1. General description The 74AUP1G00 provides the single 2-input NAND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall


    Original     		PDF 74AUP1G00 74AUP1G00 74AUP1G00GW 74AUP1G00GF 74AUP1G00GM

    74AUP1G34

    Abstract: 74AUP1G34GF 74AUP1G34GM 74AUP1G34GW
    Text: 74AUP1G34 Low-power buffer Rev. 4 — 14 July 2010 Product data sheet 1. General description The 74AUP1G34 provides a low-power, low-voltage single buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.


    Original     		PDF 74AUP1G34 74AUP1G34 74AUP1G34GF 74AUP1G34GM 74AUP1G34GW

    74AUP1T34GF

    Abstract: 74AUP1T34GM MO-203
    Text: 74AUP1T34 Low-power dual supply translating buffer Rev. 2 — 19 August 2010 Product data sheet 1. General description The 74AUP1T34 provides a single buffer with two separate supply voltages. Input A is designed to track VCC A . Output Y is designed to track VCC(Y). Both, VCC(A) and VCC(Y)


    Original     		PDF 74AUP1T34 74AUP1T34 74AUP1T34GF 74AUP1T34GM MO-203

    JESD22-A114E

    Abstract: No abstract text available
    Text: 74AUP1G09 Low-power 2-input AND gate with open-drain Rev. 2 — 9 July 2010 Product data sheet 1. General description The 74AUP1G09 provides the single 2-input AND gate with an open-drain output. The output of the device is an open-drain and can be connected to other open-drain outputs to


    Original     		PDF 74AUP1G09 74AUP1G09 JESD22-A114E

    74AUP1G0832

    Abstract: 74AUP1G0832GF 74AUP1G0832GM 74AUP1G0832GW
    Text: 74AUP1G0832 Low-power 3-input AND-OR gate Rev. 3 — 5 October 2010 Product data sheet 1. General description The 74AUP1G0832 provides the Boolean function: Y = A x B + C. The user can choose the logic functions OR, AND and AND-OR. All inputs can be connected to VCC or GND.


    Original     		PDF 74AUP1G0832 74AUP1G0832 74AUP1G0832GF 74AUP1G0832GM 74AUP1G0832GW

    3-input orgate

    Abstract: SOT-120 74AUP1G332 74AUP1G332GF 74AUP1G332GM 74AUP1G332GW
    Text: 74AUP1G332 Low-power 3-input OR-gate Rev. 3 — 7 October 2010 Product data sheet 1. General description The 74AUP1G332 provides a single 3-input OR gate. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.


    Original     		PDF 74AUP1G332 74AUP1G332 3-input orgate SOT-120 74AUP1G332GF 74AUP1G332GM 74AUP1G332GW

    74AUP1G58L6X

    Abstract: 74AUP1G58 74AUP1G58FHX JESD22-A114 xnor
    Text: 74AUP1G58 TinyLogic Low Power Universal Configurable Two-Input Logic Gate Features Description ƒ ƒ 0.8V to 3.6V VCC Supply Operation ƒ High Speed tPD - 3.1ns: Typical at 3.3V ƒ ƒ Power-Off High-Impedance Inputs and Outputs The 74AUP1G58 is a universal configurable 2-input


    Original     		PDF 74AUP1G58 74AUP1G58 74AUP1G58L6X 74AUP1G58FHX JESD22-A114 xnor

    Untitled

    Abstract: No abstract text available
    Text: 74AUP1G126 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed (Top View) for low power and extended battery life in portable applications. The 74AUP1G126 is a single non-inverting buffer/bus driver designed


    Original     		PDF 74AUP1G126 74AUP1G126 OT353 DS35158

    74AUP1G86SE

    Abstract: No abstract text available
    Text: 74AUP1G86 SINGLE 2 INPUT EXCLUSIVE-OR GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G86 is a single 2-input positive exclusive-OR gate with a


    Original     		PDF 74AUP1G86 74AUP1G86 DS35156 74AUP1G86SE

    Untitled

    Abstract: No abstract text available
    Text: 74AUP1G38 Low-power 2-input NAND gate open drain Rev. 01 — 20 October 2006 Product data sheet 1. General description The 74AUP1G38 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.


    Original     		PDF 74AUP1G38 74AUP1G38

    74AUP1G58

    Abstract: 74AUP1G58GF 74AUP1G58GM
    Text: 74AUP1G58 Low-power configurable multiple function gate Rev. 4 — 11 October 2010 Product data sheet 1. General description The 74AUP1G58 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,


    Original     		PDF 74AUP1G58 74AUP1G58 74AUP1G58GF 74AUP1G58GM

    74AUP1G14

    Abstract: 74AUP1G14GF 74AUP1G14GM 74AUP1G14GW MO-203
    Text: 74AUP1G14 Low-power Schmitt trigger inverter Rev. 4 — 13 July 2010 Product data sheet 1. General description The 74AUP1G14 provides a single inverting Schmitt trigger which accepts standard input signals. It is capable of transforming slowly changing input signals into sharply defined,


    Original     		PDF 74AUP1G14 74AUP1G14 74AUP1G14GF 74AUP1G14GM 74AUP1G14GW MO-203

    74AUP1G17

    Abstract: 74AUP1G17GF 74AUP1G17GM 74AUP1G17GW MO-203
    Text: 74AUP1G17 Low-power Schmitt trigger Rev. 4 — 15 July 2010 Product data sheet 1. General description The 74AUP1G17 provides the single Schmitt-trigger buffer. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.


    Original     		PDF 74AUP1G17 74AUP1G17 74AUP1G17GF 74AUP1G17GM 74AUP1G17GW MO-203

    JESD22-C101E

    Abstract: No abstract text available
    Text: Demonstrate seven different logic functions NXP demo board for the configurable logic device 74AUP1T97 NXP demo board for the configurable logic device 74AUP1T97 Key features and benefits } Wide supply voltage range: 2.3 to 3.6 V } High noise immunity } Excellent ESD protection


    Original     		PDF 74AUP1T97 JESD22-A114F JESD22-A115-A JESD22-C101E

    74AUP1G57

    Abstract: 74AUP1G57GF 74AUP1G57GM 74AUP1G57GW JESD22-A114-C transistor VT 209 M CDM 12.6 Philips
    Text: 74AUP1G57 Low-power configurable multiple function gate Rev. 01. — 16 January 2006 Preliminary data sheet 1. General description The 74AUP1G57 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.


    Original     		PDF 74AUP1G57 74AUP1G57 74AUP1G57GF 74AUP1G57GM 74AUP1G57GW JESD22-A114-C transistor VT 209 M CDM 12.6 Philips

    74AUP1G332

    Abstract: 74AUP1G332GF 74AUP1G332GM 74AUP1G332GW JESD22-A114-C
    Text: 74AUP1G332 Low-power 3-input OR gate Rev. 01.00 — 27 February 2006 Preliminary data sheet 1. General description The 74AUP1G332 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall


    Original     		PDF 74AUP1G332 74AUP1G332 74AUP 74AUP1G332GF 74AUP1G332GM 74AUP1G332GW JESD22-A114-C

    Untitled

    Abstract: No abstract text available
    Text: 74AUP1G58 TinyLogic Low Power Universal Configurable Two-Input Logic Gate Features Description ̇ ̇ 0.8V to 3.6V VCC Supply Operation ̇ High Speed tPD - 3.1ns: Typical at 3.3V ̇ ̇ Power-Off High-Impedance Inputs and Outputs The 74AUP1G58 is a universal configurable 2-input


    Original     		PDF 74AUP1G58 74AUP1G58

    74AUP1G00

    Abstract: 74AUP1G00GM 74AUP1G00GW JESD22-A114-C MO-203 SC88A
    Text: 74AUP1G00 Low-power 2-input NAND gate Rev. 01 — 11 July 2005 Product data sheet 1. General description The 74AUP1G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall


    Original     		PDF 74AUP1G00 74AUP1G00 74AUP1G00GM 74AUP1G00GW JESD22-A114-C MO-203 SC88A

    74AUP1G158GF

    Abstract: 74AUP1G158GM 74AUP1G158GW JESD22-A114E
    Text: 74AUP1G158 Low-power 2-input multiplexer; inverting Rev. 02 — 2 July 2009 Product data sheet 1. General description The 74AUP1G158 is a single 2-input multiplexer which select data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data


    Original     		PDF 74AUP1G158 74AUP1G158 74AUP1G158GF 74AUP1G158GM 74AUP1G158GW JESD22-A114E