Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    74LS74 Search Results

    74LS74 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74LS74AFPEL-E Renesas Electronics Corporation HD74LS Series Visit Renesas Electronics Corporation
    74LS74AP-E Renesas Electronics Corporation HD74LS Series Visit Renesas Electronics Corporation
    HD74LS74ARP Renesas Electronics Corporation Dual D-Type Positive Edge-triggered Flip-Flops (with Preset and Clear), , / Visit Renesas Electronics Corporation
    SN74LS74ADRG4 Texas Instruments Dual D-type pos.-edge-triggered flip-flops with preset and clear 14-SOIC 0 to 70 Visit Texas Instruments Buy
    SN74LS74ANSRG4 Texas Instruments Dual D-type pos.-edge-triggered flip-flops with preset and clear 14-SO 0 to 70 Visit Texas Instruments Buy
    SF Impression Pixel

    74LS74 Price and Stock

    Rochester Electronics LLC DM74LS74ASJX

    D FLIP-FLOP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey DM74LS74ASJX Bulk 8,000 2,959
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 $0.1
    		Buy Now

    Rochester Electronics LLC SN74LS74AML1

    IC FLIP FLOP D-TYPE
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74LS74AML1 Bulk 6,000 2,664
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 $0.11
    		Buy Now

    Rochester Electronics LLC SN74LS74AM

    FLIP FLOP D-TYPE POS-EDGE
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74LS74AM Bulk 4,500 2,959
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 $0.1
    		Buy Now

    Rochester Electronics LLC SN74LS74ANS

    D-TYPE POS TRG DUAL 14SO
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74LS74ANS Bulk 4,050 1,268
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 $0.24
    		Buy Now

    Rochester Electronics LLC SN74LS74AD

    SN74LS74A DUAL D-TYPE POS.-EDGE-
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74LS74AD Bulk 3,595 587
    • 1 -
    • 10 -
    • 100 -
    • 1000 $0.51
    • 10000 $0.51
    		Buy Now
    Find more 74LS74 price and stock on Findchips.com

    74LS74 Datasheets (17)

    Part ECAD Model Manufacturer Description Curated Type PDF
    74LS74 Fairchild Semiconductor Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Original PDF
    74LS74 Hitachi Semiconductor Dual D-type Positive Edge-triggered Flip-Flops(With Preset and Clear) Original PDF
    74LS74 Motorola DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP Original PDF
    74LS74 National Semiconductor Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Original PDF
    74LS74 On Semiconductor LOW POWER SCHOTTKY Original PDF
    74LS74 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    74LS74 Raytheon Dual D-Type Positive-Edge-Triggered Flip-Flop Scan PDF
    74LS74 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    74LS74A Unknown 54LS74A Original PDF
    74LS74A Texas Instruments DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR Original PDF
    74LS74A Signetics Dual D-Type Flip-Flop Scan PDF
    74LS74A Signetics Dual D-Type Flip-Flop Scan PDF
    74LS74C Unknown TTL Data Book 1980 Scan PDF
    74LS74DC Fairchild Semiconductor Dual D-Type Positive Edge Triggered Flip-Flop Scan PDF
    74LS74FC Fairchild Semiconductor Dual D-Type Positive Edge Triggered Flip-Flop Scan PDF
    74LS74M Unknown TTL Data Book 1980 Scan PDF
    74LS74PC Fairchild Semiconductor Dual D-Type Positive Edge Triggered Flip-Flop Scan PDF

    74LS74 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74LS147

    Abstract: 74ls147 pin diagram FUNCTIONAL APPLICATION OF 74LS148 74ls148 74LS147 equivalent motorola 74ls147 74ls748 SN54/74LS147 FAST AND LS TTL ls74
    Text: SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54/ 74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are


    Original     		PDF SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE 74LS147 74LS148 LS147 LS148 74ls147 pin diagram FUNCTIONAL APPLICATION OF 74LS148 74LS147 equivalent motorola 74ls147 74ls748 SN54/74LS147 FAST AND LS TTL ls74

    74ls74a

    Abstract: 751A-02
    Text: SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs.


    Original     		PDF SN54/74LS74A 74LS74A 751A-02

    74LS74A

    Abstract: 751A-02
    Text: SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs.


    Original     		PDF SN54/74LS74A 74LS74A 751A-02

    74LS147

    Abstract: 74ls147 pin diagram 74ls748 SN54/74LS147,SN54/74LS148 74LS148 motorola 74ls147 PIN 74LS147 74ls147 datasheet 74LS147 equivalent LS148
    Text: SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54 / 74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are


    Original     		PDF SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE 74LS147 74LS148 LS147 LS148 LS148) LS748) 74ls147 pin diagram 74ls748 SN54/74LS147,SN54/74LS148 motorola 74ls147 PIN 74LS147 74ls147 datasheet 74LS147 equivalent

    TC74HC74AP

    Abstract: TC74HC74A
    Text: TC74HC74AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC74AP,TC74HC74AF Dual D-Type Flip Flop Preset and Clear The TC74HC74A is a high speed CMOS D FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent


    Original     		PDF TC74HC74AP/AF TC74HC74AP TC74HC74AF TC74HC74A TC74HC74AP

    MC2100 REV B

    Abstract: MC2100 REV c 74109 MC2100 e rev b MC2100 Rev A MC212 MC2100 MC2300 MC2400 MC2500
    Text: Navigator Motion Processor MC2100 Series Technical Specifications for Brushed Servo Motion Control Performance Motion Devices, Inc. 55 Old Bedford Road Lincoln, MA 01773 Revision 1.6, April 2002 NOTICE This document contains proprietary and confidential information of Performance Motion Devices,


    Original     		PDF MC2100 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 CP2N40 UI0-10 UI0-11 MC2100 REV B MC2100 REV c 74109 MC2100 e rev b MC2100 Rev A MC212 MC2300 MC2400 MC2500

    F7474PC

    Abstract: 74ls74d 7474 pin out diagram ic 7474 pin diagram 74H74D 7474PC IC 74LS74 pin IC 7474 74LS74PC IC 7474 flipflop
    Text: 74 C O N N E C T IO N DIAGRAM S P IN O U T A 54/7474 < ? / / 6 ' \/54H/74H74 t f e. j w w^4S/74S74 £>/, o 'b, U34LS/74LS74 ^ ^ < - 3 ^ — "Si / / DUAL D-TYPE POSITIVE ED G e"TRIGGERED FLIP-FLOP P IN O U T B DESCRIPTIO N — The ’74 devices are dual D-type flip-flops with Direct C le a r


    OCR Scan     		PDF \/54H/74H74 4S/74S74 34LS/74LS74 54/74H 54/74S 54/74LS F7474PC 74ls74d 7474 pin out diagram ic 7474 pin diagram 74H74D 7474PC IC 74LS74 pin IC 7474 74LS74PC IC 7474 flipflop

    LS748

    Abstract: 74LS147 74LS148 74lS748
    Text: g MOTOROLA SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The S N 54/74LS 147 and the SN 54/74LS 148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order


    OCR Scan     		PDF 10-LINE-TO-4-LINE 54/74LS LS147 LS148 SN54/74LS148 SN54/74LS748 LS148) LS748) LS748 74LS147 74LS148 74lS748

    Untitled

    Abstract: No abstract text available
    Text: H D 74LS74A . Dual D-type Positive Edge-triggered Flip-Flops with Preset and Clear • P IN ARRANGEMENT ■FU N C T IO N TABLE O utputs Inputs P re s e t C lear Clock D Q Q L H X X H L H L X X L H L L X X H* H* H H H H L H H L L H H H X Qo Qo L Notes) H; high level, L; low level, X; irrelevant


    OCR Scan     		PDF HD74LS74A T-90-10 74LSOO ib203

    74LS74A

    Abstract: 54LS 74LS
    Text: GD54/74LS74A DUAL D-TYPE POS.T.VE EDGE-TRIGGED FLIP-FLOPS Description Pin Configuration This device contains tw o ind epen den t D -typ e positive ed g e triggered flip-flops. A low level at the p reset or clear inputs sets or resets the outputs regardless of the levels of the


    OCR Scan     		PDF GD54/74LS74A configurat25Â 74LS74A 54LS 74LS

    74LS147

    Abstract: 74LS148 PIN 74LS147
    Text: M MOTOROLA D ESCRIPTIO N — The S N 5 4 L S /7 4 L S 147 and th e S N 54 L S /7 4 L S 148 SN54LS/74LS147 SN54LS/74LS148 SN54LS/74LS748 are Priority Encoders. They provide prio rity decoding of the inputs to ensure th a t only th e highest order data line is encoded. Both devices


    OCR Scan     		PDF LS147 LS148 54LS74LS143 LS148) LS748) 74LS147 74LS148 PIN 74LS147

    74LS74A

    Abstract: No abstract text available
    Text: <g> MOTOROLA SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The S N 54/74LS 74A dual edge-triggered flip-flop utilizes Schottky TTL cir­ cuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also com plementary Q and Q outputs.


    OCR Scan     		PDF SN54/74LS74A 54/74LS 74LS74A

    74LS147

    Abstract: 74LS148 74ls748 LS748 PIN 74LS147 LS148 ttl 74ls147 LS 74LS147 6200S ttl 74ls148
    Text: <8 > MOTOROLA SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The S N 54/74LS 147 and the S N 54/74LS 148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order


    OCR Scan     		PDF 10-LINE-TO-4-LINE 54/74LS LS147 LS148 SN54/74LS148 SN54/74LS748 LS148) LS748) 74LS147 74LS148 74ls748 LS748 PIN 74LS147 ttl 74ls147 LS 74LS147 6200S ttl 74ls148

    74LS74 truth table

    Abstract: 7474PC 74LS74PC pin IC 7474 DE flip-flop 7474 74ls74d 74S74 national 74ls74 ic logic diagram of ic 7474 54LS74FM
    Text: NATIONAL SENICOND -CLOGIO D2E D | LSDllES D0b371S 2 | 74 T-46-07-09 CO NNECTIO N DIAGRAM S PINO UT A 54/7474 54H/74H74 54S/74S74 54LS/74LS74 DUAL D-TYPE POSITIVE EDGETRIG GERED FLIP-FLOP PINO UT B DESCRIPTION — The '74 devices are dual D-type flip -flo p s w ith Direct Clear


    OCR Scan     		PDF D0b371S T-46-07-09 54H/74H74 54S/74S74 54LS/74LS74 QDb3717 54/74H 54/74S 54/74LS 74LS74 truth table 7474PC 74LS74PC pin IC 7474 DE flip-flop 7474 74ls74d 74S74 national 74ls74 ic logic diagram of ic 7474 54LS74FM

    74LS74A

    Abstract: No abstract text available
    Text: M M O T O R O L A SN54/74LS74A D E S C R I P T I O N - The S N 5 4 L S /7 4 L S 7 4 A dual edge-triggered flip-flop u tilizes Schottky TTL circu itry to produce high speed D-type flip-flops. Each flip-flop has individual cfear and set inputs, arid also com plem entary


    OCR Scan     		PDF SN54/74LS74A 74LS74A

    Untitled

    Abstract: No abstract text available
    Text: GD54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERD FLIP-FLOPS W ITH PRESET AND CLEAR Description Pin Configuration This device contains two independent D-type positive edge triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the


    OCR Scan     		PDF GD54/74LS74A DGGU21S

    d1410

    Abstract: TTL 74LS74 IC 74LS74 74ls74 LC74HC74
    Text: L N al C 7 H 4 6 9 5b c C 7 4 te m o s / V D u a l D - T y p e w i t h F l i p - F l o p R e s e t a n d S e t N d l 695a » LC74HC74 \t D ^ < 7 7>;v7 •CM O SS'Vd^-I^ 7ü-t^ T *$ Ç 7 □ 7 7 L I 'V LS-TO j 74LS74 * § ^ « W f l ï A t f - h' ^ 7 7 7 i< m o ? .n r ^ o


    OCR Scan     		PDF LC74HC74 Nfll695a LC74HC74 74LS74) 54LS/74LS LC74HC74) -Jt-50 d1410 TTL 74LS74 IC 74LS74 74ls74

    74ls74 pin configuration

    Abstract: 7474 D flip-flop S5474F 74H74 7474 D flip flop 74ls74 N7474F pin diagram of 7474 S54S74F/883B N74H74F
    Text: 54/7474 54H/74H74 54S/74S74 54LS/74LS74 DESCRIPTION Th e “ 74” is a Dual P ositive E dge -T rig gere d D -T ype F lip-F lo p fe a tu rin g ind ivid u a l data, c lo c k , set and reset inputs; also c o m p le ­ m e ntary Q and Q ou tp u ts. S et S d and Reset (R d ) are a syn ch ro n o u s


    OCR Scan     		PDF 54H/74H74 54S/74S74 54LS/74LS74 54H/74H 54S/74S 54LS/74LS 74ls74 pin configuration 7474 D flip-flop S5474F 74H74 7474 D flip flop 74ls74 N7474F pin diagram of 7474 S54S74F/883B N74H74F

    74LS299 APPLICATIONS

    Abstract: 74ls74 timing setup hold pin diagram and block diagram of 74ls74 ANSI32
    Text: TMS320SA32 32 KBIT/S ADPCM TRANSCODER NOVEMBER 1986 N PACKAGE ANSI 32 kbit/s ADPCM Compatible TOP VIEW CCITT G.721 32 kbit/s ADPCM Compatible Half-Duplex Transcoder Operation Transmit/Receive Selection Option /t-Law/A-Law PCM Selection Option NC£ 1^ 4 0 □


    OCR Scan     		PDF TMS320SA32 165-mW 74LS299 APPLICATIONS 74ls74 timing setup hold pin diagram and block diagram of 74ls74 ANSI32

    74ls74a ic

    Abstract: SN54L74
    Text: TYPES SN5474, SN54H74, SN54L74, SN54LS74A, SN54S74, SN7474, SN74H74, 74LS74A, SN74S74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR R E V IS E D D E C E M B E R 1983 Package Options Include Both Plástic and Ceram ic Chip Carriers in Addition to Plastic


    OCR Scan     		PDF SN5474, SN54H74, SN54L74, SN54LS74A, SN54S74, SN7474, SN74H74, SN74LS74A, SN74S74 74ls74a ic SN54L74

    TMP68661

    Abstract: No abstract text available
    Text: TOSHIBA UC/UP S4E D • c]0,ì 7 2 4 Iì G 0 5 4 G 7 5 TO SHIBA Ö24 * T 0 S 3 TM P68661 1. INTRODUCTION - r - is - 3 1 - a n The TMP68661 enhanced program m able communications interface (EPCI) is a universal synchoronous/asynchronous data communications controller chip th at is an


    OCR Scan     		PDF G054G75 P68661 TMP68661 TMP68000 16-bit 54BSC 24BSC

    74hc74a

    Abstract: plj1 TC74HC74
    Text: - TC74HC74AP/AF/AFN D U A L D - T Y P E F L I P FLOP PRESET A N D C L EA R T h e T C 74H C 74A is a h ig h spe ed CM O S D F L I P F L O P f a b r i c a t e d w i t h s i l i c o n g a t e C 2M O S t e c h n o l o g y . I t a c h i e v e s t h e h i g h s p e e d o p e r a t i o n s i m i l a r to


    OCR Scan     		PDF TC74HC74AP/AF/AFN 74hc74a plj1 TC74HC74

    Untitled

    Abstract: No abstract text available
    Text: •i TC74HC74AP/AF/AFN D U A L D - T Y P E F L I P FLOP P RE S E T A N D C L E A R T h e T C 7 4 H C 7 4 A is a h ig h speed C M O S D F L I P FLO P fa b r ic a te d w ith s ilic o n g a te C 'M O S te c h n o lo g y . It a ch ie ve s the h igh speed o p e ra tio n


    OCR Scan     		PDF TC74HC74AP/AF/AFN TC74HC74AP/AF/AFN-3 TC74HC74AP/AF/AFN-4

    Untitled

    Abstract: No abstract text available
    Text: y T C 7 4 H C T 7 4 A P / A F D U A L D - T Y P E F L I P F L O P WI TH P R E S E T AND C L E A R T h e T C 7 4 H C T 7 4 A is a h ig h speed C M O S D K L I P F L O P fa b r ic a te d w ith s ilic o n g a te C 'M O S te c h n o lo g y . It a ch ie v e s the


    OCR Scan     		PDF TC74HCT74AP/AF-3 TC74HCT74AP/AF-4