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    74LS109 Search Results

    74LS109 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SN74LS109ADR Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC 0 to 70 Visit Texas Instruments
    SN74LS109ANSR Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-SO 0 to 70 Visit Texas Instruments Buy
    SN74LS109AD Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC 0 to 70 Visit Texas Instruments Buy
    SN74LS109ANE4 Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-PDIP 0 to 70 Visit Texas Instruments Buy
    SN74LS109AN Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-PDIP 0 to 70 Visit Texas Instruments Buy
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    74LS109 Price and Stock

    Rochester Electronics LLC SN74LS109ADR

    IC FF JK TYPE DUAL 1BIT 16SOIC
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74LS109ADR Bulk 30,000 488
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    Rochester Electronics LLC SN74LS109ANSR

    SN74LS109A DUAL J-K POSITIVE-EDG
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74LS109ANSR Bulk 20,000 390
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    Texas Instruments SN74LS109ANSR

    IC FF JK TYPE DUAL 1BIT 16SO
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    DigiKey SN74LS109ANSR Cut Tape 1,910 1
    • 1 $1.59
    • 10 $1.427
    • 100 $1.1466
    • 1000 $0.78058
    • 10000 $0.78058
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    SN74LS109ANSR Digi-Reel 1
    • 1 $1.59
    • 10 $1.427
    • 100 $1.1466
    • 1000 $0.78058
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    SN74LS109ANSR Reel 2,000
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    Mouser Electronics SN74LS109ANSR
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    Rochester Electronics SN74LS109ANSR 20,000 1
    • 1 $0.7773
    • 10 $0.7773
    • 100 $0.7307
    • 1000 $0.6607
    • 10000 $0.6607
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    Texas Instruments SN74LS109AN

    IC FF JK TYPE DUAL 1BIT 16DIP
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    DigiKey SN74LS109AN Tube 623 1
    • 1 $1.16
    • 10 $1.042
    • 100 $0.8378
    • 1000 $0.6925
    • 10000 $0.6925
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    Mouser Electronics SN74LS109AN 1,177
    • 1 $1.16
    • 10 $0.984
    • 100 $0.786
    • 1000 $0.692
    • 10000 $0.692
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    Newark SN74LS109AN Bulk 367 1
    • 1 $2.12
    • 10 $1.97
    • 100 $1.65
    • 1000 $1.54
    • 10000 $1.54
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    Bristol Electronics SN74LS109AN 4
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    Jameco Electronics SN74LS109AN Each 278 1
    • 1 $1.45
    • 10 $1.25
    • 100 $1.05
    • 1000 $1.05
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    Rochester Electronics SN74LS109AN 16,547 1
    • 1 $0.8079
    • 10 $0.8079
    • 100 $0.7594
    • 1000 $0.6867
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    ComSIT USA SN74LS109AN 171
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    Chip 1 Exchange SN74LS109AN 620
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    Component Electronics, Inc SN74LS109AN 611
    • 1 $0.5
    • 10 $0.5
    • 100 $0.38
    • 1000 $0.33
    • 10000 $0.33
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    Texas Instruments SN74LS109AD

    IC FF JK TYPE DUAL 1BIT 16SOIC
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74LS109AD Tube 569 1
    • 1 $1.71
    • 10 $1.539
    • 100 $1.452
    • 1000 $1.01631
    • 10000 $1.01631
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    Rochester Electronics SN74LS109AD 25,060 1
    • 1 $0.8385
    • 10 $0.8385
    • 100 $0.7882
    • 1000 $0.7127
    • 10000 $0.7127
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    Ameya Holding Limited SN74LS109AD 2,206
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    Find more 74LS109 price and stock on Findchips.com

    74LS109 Datasheets (9)

    Part ECAD Model Manufacturer Description Curated Type PDF
    74LS109 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    74LS109 Raytheon Dual J-K Posilive-Edge-Triggered Flip-Flop Scan PDF
    74LS109 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    74LS109A Signetics Dual J-K Positive Edge-Triggered Flip-Flop Scan PDF
    74LS109A Signetics Flip-Flops Scan PDF
    74LS109C Unknown TTL Data Book 1980 Scan PDF
    74LS109DC Fairchild Semiconductor Dual JK Positive Edge Triggered Flip-Flop Scan PDF
    74LS109FC Fairchild Semiconductor Dual JK Positive Edge Triggered Flip-Flop Scan PDF
    74LS109PC Fairchild Semiconductor Dual JK Positive Edge Triggered Flip-Flop Scan PDF

    74LS109 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    SN54/74LS109A

    Abstract: 751B-03 truth table NOT gate 74 74LS109A SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74ls109
    Text: SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D


    Original     		PDF SN54/74LS109A 74LS109A 751B-03 SN54/74LS109A 751B-03 truth table NOT gate 74 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74ls109

    74LS109A

    Abstract: SN54/74LS109A SN54LSXXXJ SN74LSXXXD SN74LSXXXN 751B-03
    Text: SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D


    Original     		PDF SN54/74LS109A 74LS109A 751B-03 SN54/74LS109A SN54LSXXXJ SN74LSXXXD SN74LSXXXN 751B-03

    transistor NEC K2500

    Abstract: nec k2500 NEC K2500 Transistor component NEC K2500 mosfet CD4558 cq met t3.15A 250V k2500 N-Channel MOSFET c5042f TO-92 78L05 voltage regulator pin configuration i ball 450 watt smps repairing
    Text: A merican Gaming and Electronics, Inc. represents over 200 vendors and carries thousands of items. This catalog is just a partial listing of our products. If for any reason, you do not see the item s you are searching for, please call your local sales representative. The sales


    Original     		PDF

    CI 7474

    Abstract: CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 fairchild 9024 ci 74LS74 74ls107
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 ui 9 D UJ 5 -=pi (3 J Q 2 — J SD 0 CP Z o (3 11 4 K Ä 0 Co “LT in > _6 12 CP 3 -0 14 K Co ° 7 o-i- CP 13 —c K Cd °


    OCR Scan     		PDF 54S/74S109, 54LS/74LS109 54H/74H74, 54S/74S74, 54LS/74LS74 54H/74H73, 54LS/74LS279 93L14 54LS/74LS196 54LS/74LS197 CI 7474 CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 fairchild 9024 ci 74LS74 74ls107

    74LS109PC

    Abstract: No abstract text available
    Text: 109 C O N N E C T IO N D IA G R A M PINOUT A /54S /74S 109 v o4LS/74LS109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP D E S C R IP T IO N — The '109 consists of tw o high speed, com pletely indepen­ dent transition clocked J K flip-flops. The clocking operation is independent


    OCR Scan     		PDF o4LS/74LS109 54/74S 54/74LS 74LS109PC

    74LS109A

    Abstract: SN54/74LS109A truth table NOT gate 74
    Text: M M O T O R O L A SN54/74LS109A D E S C R IP T IO N — T h e S N 5 4 L S /7 4 L S 1 0 9 A c o n s is ts of tw o hig h speed c o m p le te ly in d e p e n d e n t tra n s itio n clo cked J K flip -flo p s . T he clo c k in g o p e ra tio n is in d e p e n d e n t o f rise and fa ll tim e s o f th e c lo c k w a v e fo rm . The


    OCR Scan     		PDF SN54LS/74LS109A SN54/74LS109A Inp125 74LS109A SN54/74LS109A truth table NOT gate 74

    Untitled

    Abstract: No abstract text available
    Text: M M O TO R O LA SN54/74LS109A D E S C R IP T IO N — The S N 5 4 L S /7 4 L S 10 9 A consists o f tw o high speed com pletely independent tra n sitio n clocked JK flip-flops. The clocking operation is independent of rise and fa ll tim es o f th e d o c k w aveform . The


    OCR Scan     		PDF SN54/74LS109A

    74LS109

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series 74LS109 D N 7 4 L S 1 0 9 Dual J-K Positive Edge-Triggered Flip-Flops with Set and Reset P-2 • Description DN 74LS109 contains tw o positive-edge triggered J-K flipflop circuits, each w ith independent clock-CP, J, K, and direct-coupled set and reset input terminals.


    OCR Scan     		PDF DN74LS DN74LS109 74LS109 16-pin Zwit-500 MA161

    Untitled

    Abstract: No abstract text available
    Text: GD54/74LS109A DUAL POSITIVE-EDGE- TRIGGERED J-K FLIP-FLOPS Feature Pin Configuration • Positive Edge-Triggering • Direct Set and reset inputs • J and K inputs • Q and Q outputs Vcc CLR2 J2 K2 C LK 2 PR2 Q2 QS R RRRFI R HR y Description This device contains two independent positiveedge-triggered J-K flip-flops with complementary out­


    OCR Scan     		PDF GD54/74LS109A

    74ls109

    Abstract: No abstract text available
    Text: MOTOROLA SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP T h e S N 5 4 /7 4 L S 1 0 9 A c o n sists of tw o high sp e e d c o m p le te ly in d e p e n d e n t tra n s itio n clo cke d JK flip -flo p s. T h e c lo c k in g o p e ra tio n is in d e p e n d e n t o f rise


    OCR Scan     		PDF SN54/74LS109A 751B-03 74ls109

    TTL 74ls74

    Abstract: 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 5 ui 9 D UJ -=pi (3 J Q 2 — J SD 0 CP Z o (3 4 K Ä Co “LT in > </> O a 3 -0 K Co ° I- 3 a. I- 3 O 4-0 Co ? 15 D61 54/7474, 54H/74H74,


    OCR Scan     		PDF 54S/74S109, 54LS/74LS109 54H/74H74, 54S/74S74, 54LS/74LS74 54H/74H73, 54H/74H73 54H/74H103 54S/74S113 54LS/74LS113 TTL 74ls74 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN

    74LSOO

    Abstract: HD74LS109A
    Text: H D 74LS109A . Dual J-K Positive-edge-triggered Flip-Flops with Preset and Clear IP IN ARRANGEMENT •REC O M M EN D ED OPERATING CONDITIONS S ym bol Item fr o c k C lock fre q u e n c y C lo c k High P u ls e w idth S r'.v lo w “ H " D a ta S e tu p tim e


    OCR Scan     		PDF HD74LS109A. QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 74LSOO HD74LS109A

    TTL 74ls74

    Abstract: 7474 14 PIN 74ls76 7476 ttl ttl 74ls109 74LS107 74LS73 74ls74 TTL 74ls76 74LS109
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL M A S T E R /S LA V E E D G E -T R IG G E R E D D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 ui 9 D UJ 5 -=pi J Q (3 CP o K Z 2 — J SD 0 _6 Co (3 “LT in > z o Q J CP I- 3 a. 3 O So J - Ö K 4-0


    OCR Scan     		PDF 54S/74S109, 54LS/74LS109 54H/74H74, 54S/74S74, 54LS/74LS74 54H/74H73, 54L15 TTL 74ls74 7474 14 PIN 74ls76 7476 ttl ttl 74ls109 74LS107 74LS73 74ls74 TTL 74ls76 74LS109

    RS flip flop IC

    Abstract: M74LS109AP T flip flop pin configuration Toggle flip flop IC JK flip flop IC 20-PIN toggle type flip flop ic
    Text: MITSUBISHI LSTTLs M 74LS109AP DUAL J-K POSITIVE EDGE-TRIGGERED FLIP FLO P WITH S E T AND R ESE T DESCRIPTION PIN C O NFIG URATIO N TOP V IEW The 74LS109AP is a semiconductor integrated circuit containing 2 J-K positive edge-triggered flip-flop circuits


    OCR Scan     		PDF M74LS109AP M74LS109AP 16-PIN 20-PIN RS flip flop IC T flip flop pin configuration Toggle flip flop IC JK flip flop IC toggle type flip flop ic

    Untitled

    Abstract: No abstract text available
    Text: H D 74LS109A . •REC O M M EN D ED OPERATING Symbol Item /„O 'k Clock frequency Clock High P u lse width Sr.*.v* low “H "D ata Setup tim e “ L 'D a ta th Hold tim e Note 11 The arrow indicates the rising edge. Dual J-K Positive-edge-triggered Flip-Flops with Preset and Clear)


    OCR Scan     		PDF 74LS109A T-90-10 74LSOO ib203

    74LSOO

    Abstract: 1S2074 HD74LS109A HD74LS109
    Text: H D 74LS109A . Dual J-K Positive-edge-triggered Flip-Flops with Preset and Clear IP IN ARRANGEMENT •REC O M M EN D ED OPERATING CONDITIONS S ym bol Item fro c k C lock fre q u e n c y C lo c k High P u ls e w idth Sr.*.v* low “ H " D a ta S e tu p tim e


    OCR Scan     		PDF HD74LS109A. QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 74LSOO 1S2074 HD74LS109A HD74LS109

    pin diagram of 74109

    Abstract: 74109 74109 dual JK PIN CONFIGURATION 74109 TTL 74109 1N3064 1N916 74LS 74LS109 74LS109A
    Text: 74109, LS109A Signetics Flip-Flops Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Logic Products TYPICAL f MAX TYPICAL SUPPLY CURRENT TOTAL 74109 33MHz 9mA 74LS109A 33MHz 4mA DESCRIPTION The '109 is dual positive edge-triggered JK-type flip-flop featuring individual J, K,


    OCR Scan     		PDF LS109A 1N916, 1N3064, 500ns pin diagram of 74109 74109 74109 dual JK PIN CONFIGURATION 74109 TTL 74109 1N3064 1N916 74LS 74LS109 74LS109A

    74LS109D

    Abstract: 4151 cp IR 9024 74LS109PC 74S109
    Text: I 1 NATIONAL SEMICOND -CLOGIO OSE D 1 5 0 1 1 5 2 □Dt,37flS 1 | T~ ¥ 6 - 0 7 - 0 7 109 C O N N E C T IO N D IA G R A M P IN O U T A 54S/74S109 54LS/74LS109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP D E S C R IP T IO N — T he ’109 co n sists of two high speed, com pletely indepen­


    OCR Scan     		PDF 37flS 54S/74S109 54LS/74LS109 54/74S 54/74LS 74LS109D 4151 cp IR 9024 74LS109PC 74S109

    Untitled

    Abstract: No abstract text available
    Text: -T C 7 4 H C 1 9 A P / A F / A F N D U A L J - K F L I P - F L O P W I T H PRESET A N D C L E A R T he TC74HC109A is a hig h speed CMOS J - K F L IP F L O P


    OCR Scan     		PDF TC74HC109A TC74HC109AP/AF/AFN

    ttl 74ls109

    Abstract: 74LS109
    Text: SANYO SEM ICONDUCTOR CORP S3E ] Ordering number: EN 3897 7 T ì7 0 7 b D D 1G S 3S 7ÔE » T S A J T - HC- 0 7 - 0 7 MLC74HC109 i i SAW O CMOS High-Speed S tandard Logic Dual J-K Flip-Flop w ith Set and Reset F e a tu re s • Dual J-K flip-flop/Falling-edge triggered clock input/Active-Low reset input.


    OCR Scan     		PDF MLC74HC109 MLC74HC109 74LS109) ttl 74ls109 74LS109

    Untitled

    Abstract: No abstract text available
    Text: TOSHIBA TC74HC109AP/AF/AFN Dual J-R Flip-Flop with Preset and Clear The TC74HC109A is a high speed CMOS DUAL J-FTFUPFLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.


    OCR Scan     		PDF TC74HC109AP/AF/AFN TC74HC109A 63MHz TC74HC/HCT

    16PIN

    Abstract: 74LS109 TC74HC109AF TC74HC109AFN TC74HC109AP
    Text: TOSHIBA TC74HC109AP/AF/AFN TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC109AP, TC74HC109AF, TC74HC109AFN Note The JEDEC SOP (FN) is not available in DUAL J - K FLIP-FLOP WITH PRESET AND CLEAR Japan The TC74HC109A is a high speed CMOS J - K FLIP FLOP


    OCR Scan     		PDF TC74HC109AP/AF/AFN TC74HC109AP, TC74HC109AF, TC74HC109AFN TC74HC109A 16PIN DIP16-P-300-2 75MAX 735TYP 74LS109 TC74HC109AF TC74HC109AFN TC74HC109AP

    Untitled

    Abstract: No abstract text available
    Text: 5QE D 44^503 G01341Q 5 HITACHI/ L0GIC/ARRAYS/MÉÎ1 0 H IT A C H I S e p t e m b e r , 1985 CMOS GATE ARRAYS i HD61 SERIES DESIGNER'S MANUAL AND PRODUCT SPECIFICATION HITACHI/ LOGIC/ARR'A YS/MEM SQE D • 4 4TLS03 0G13411 4 T -42-11-09 CMOS GATE ARRAYS HD61 SERIES


    OCR Scan     		PDF G01341Q 4TLS03 0G13411 HD14070B 1407IB HD14556B HD14558B HD14560B HD14562B HD14072B

    MH1SS1

    Abstract: TESLA mh 7400 MH 7404 mh 7400 tesla cdb 838 tda 7851 L 741PC TDB0124DP tda 4100 TDA 7851 A
    Text: m ö lk ^ o e le l-c te n a n il-c Information Applikation RGW Typenübersicht Vergleich Teil 2: RGW M iM U Z A U l KÉD lnrüÖC=SraO Information Applikation HEFT 50 RGW Typenübersicht + Vergleich Teil 2: RGW wob Halbleiterwerk Frankfurt /oder bt r iab im v«b kombinat mikrootektronik


    OCR Scan     		PDF