Untitled
Abstract: No abstract text available
Text: H ig h p e r f o r m a n c e 2 5 6 / 5 12 K b y te 3.3V C ac h e m o d u le s •■ | A S 7 M 6 4 T 3 2 5 6 A A sync A S 7 M 6 4 T 3 5 1 2 A A sync R i.rct A S7M 64T3256B B u rst A S 7 M 6 4 T 3 5 1 2B B u rst Low voltage 2 5 6 /5 1 2 KByte cache modules w ith tag
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OCR Scan
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64-bit
AS7M64T32S6A
AS7M64T3512A
AS7M64T3256A
64T3512A
64T3256A-12)
60MHz*
64T3256A
3256B
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PDF
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TAG 240 400
Abstract: CELP2X80 TI06
Text: Pipelined Burst Synchronous 64 -bit Cache M o d u l e | A S7M 64U 3B Series Logic Block Diagram Features ♦ 64-bit 3.3V pipelined burst data ADSC CADV CADS CCS GWE BWE OE CLKO ♦ High speed: 6/7 ns clock access time ♦ Low power - A18 -► CE2 CE2
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OCR Scan
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32Kx32
DO-31
AO-14
D32-63
64-bit
64U3256B-13)
3256B-13)
TAG 240 400
CELP2X80
TI06
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PDF
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us8k
Abstract: d1272
Text: AS7M64T3256A AS7M64T3512A 64T3256B AS7M64T3512B B Cache Modules Async Async Burst Burst Low Voltage 256/512 KByte Cache Modules with Tag PRELIMINARY ASYNCHRONOUS VERSIONS FEATURES 64-bit 3.3V asynchronous data PIN D I A G R A M a s y n c • 5V tolerant I/O specification
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OCR Scan
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64T3256A
AS7M64T3256A
AS7M64T3512A
AS7M64T3256B
AS7M64T3512B
64-bit
T00344c
us8k
d1272
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PDF
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I007
Abstract: ST d63
Text: H ij>li | n- r I >i 11 il 11 ( i 2S6/S I l Kh\le i\ ( ' " lu " " , hl 1" I|l Im\ u iJiiijjL 2 S6 / S I l K 15y le c m lir i n n d u u il li luij Preliminary (asynchronous versions only) Logic block diagram Features • 6 4-b it 3.3V asy n chro no u s data
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OCR Scan
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64T3256A
64T35
82430FX
3256B
I007
ST d63
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PDF
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64T3A
Abstract: No abstract text available
Text: Pipelined Burst S y n c h r o n o u s | A S7M 64T3B Series 64 - bi t C a c h e M o d u l e Features Logic Block Diagram ♦ 64-bit 3.3V pipelined burst data ♦ 8-bit 5V asynchronous tag \ •wrE: 256KB o o A18 ADSC -► ADSC CADV - ► ADSP ♦ High speed: 6/7 ns clock access time
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OCR Scan
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64T3B
64-bit
1613mW
75MHz
64T3256B-13)
AS7M64T3256B-13)
256KB
32Kx32
82430FX
64T3A
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PDF
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