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    54LS74 Search Results

    54LS74 Result Highlights (4)

    Part ECAD Model Manufacturer Description Download Buy
    SNJ54LS74AJ Texas Instruments Dual D-type Positive-Edge-Triggered Flip-Flops With Preset And Clear 14-CDIP -55 to 125 Visit Texas Instruments Buy
    SNJ54LS74AFK Texas Instruments Dual D-type Positive-Edge-Triggered Flip-Flops With Preset And Clear 20-LCCC -55 to 125 Visit Texas Instruments Buy
    SNJ54LS74AW Texas Instruments Dual D-type Positive-Edge-Triggered Flip-Flops With Preset And Clear 14-CFP -55 to 125 Visit Texas Instruments Buy
    SN54LS74AJ Texas Instruments Dual D-type Positive-Edge-Triggered Flip-Flops With Preset And Clear 14-CDIP -55 to 125 Visit Texas Instruments
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    54LS74 Price and Stock

    Rochester Electronics LLC JD54LS74B2A

    DUAL D TYPE POSITIVE-EDGE-TRIGGE
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey JD54LS74B2A Bulk 320 55
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    • 100 $5.5
    • 1000 $5.5
    • 10000 $5.5
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    Rochester Electronics LLC JD54LS74SCA

    54LS74 - DUAL FLIP-FLOP, POSITIV
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey JD54LS74SCA Bulk 281 2
    • 1 -
    • 10 $228.81
    • 100 $228.81
    • 1000 $228.81
    • 10000 $228.81
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    Rochester Electronics LLC JD54LS74SDA

    54LS74 - DUAL FLIP-FLOP, POSITIV
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey JD54LS74SDA Bulk 135 2
    • 1 -
    • 10 $238.35
    • 100 $238.35
    • 1000 $238.35
    • 10000 $238.35
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    Texas Instruments SNJ54LS74AFK

    DUAL D-TYPE POSITIVE-EDGE-TRIGGE
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SNJ54LS74AFK Tube 1 1
    • 1 $13.07
    • 10 $13.07
    • 100 $13.07
    • 1000 $13.07
    • 10000 $13.07
    		Buy Now

    Texas Instruments SN54LS74AJ

    DUAL D-TYPE POSITIVE-EDGE-TRIGGE
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN54LS74AJ Tube
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    Component Electronics, Inc SN54LS74AJ 2
    • 1 $6.15
    • 10 $6.15
    • 100 $4.62
    • 1000 $4
    • 10000 $4
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    Win Source Electronics SN54LS74AJ 1,890
    • 1 -
    • 10 $13.112
    • 100 $10.653
    • 1000 $10.653
    • 10000 $10.653
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    Find more 54LS74 price and stock on Findchips.com

    54LS74 Datasheets (22)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    54LS74 National Semiconductor Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Original PDF
    54LS74 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    54LS74 Raytheon Dual D-Type Positive-Edge-Triggered Flip-Flop Scan PDF
    54LS74A Unknown 54LS74A Original PDF
    54LS74A/BCAJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS74A/BDAJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS74AM/B2AJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS74DM Fairchild Semiconductor Dual D-Type Positive Edge Triggered Flip-Flop Scan PDF
    54LS74DM Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS74DMQB National Semiconductor Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Original PDF
    54LS74DMQB Fairchild Semiconductor Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Scan PDF
    54LS74DMQB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS74DMQB National Semiconductor Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Scan PDF
    54LS74FM Fairchild Semiconductor Dual D-Type Positive Edge Triggered Flip-Flop Scan PDF
    54LS74FMQB National Semiconductor Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Original PDF
    54LS74FMQB Fairchild Semiconductor Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Scan PDF
    54LS74FMQB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS74FMQB National Semiconductor Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Scan PDF
    54LS74LMQB National Semiconductor Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Original PDF
    54LS74LMQB Fairchild Semiconductor Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Scan PDF

    54LS74 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    DM74LS74A

    Abstract: No abstract text available
    Text: 54LS74,54LS74A,DM74LS74A 54LS74 54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Literature Number: SNOS313A 54LS74 54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs


    Original     		PDF 54LS74 DM54LS74A DM74LS74A DM74LS74A SNOS313A

    Untitled

    Abstract: No abstract text available
    Text: 54LS74 54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse The triggering occurs at a


    Original     		PDF 54LS74 DM54LS74A DM74LS74A

    MAB08

    Abstract: DM74LS74AN 54LS74 54LS74DMQB 54LS74FMQB 54LS74LMQB DM54LS74A DM54LS74AJ DM54LS74AW DM74LS74A
    Text: 54LS74 54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse The triggering occurs at a


    Original     		PDF 54LS74 DM54LS74A DM74LS74A MAB08 DM74LS74AN 54LS74DMQB 54LS74FMQB 54LS74LMQB DM54LS74AJ DM54LS74AW DM74LS74A

    Untitled

    Abstract: No abstract text available
    Text: 54LS74 54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs General Description violated A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the


    Original     		PDF 54LS74 DM54LS74A DM74LS74A 14-Lead 54LS74FMQB DM54LS74AW

    Untitled

    Abstract: No abstract text available
    Text: MICROCIRCUIT DATA SHEET Original Creation Date: 04/23/98 Last Update Date: 08/24/98 Last Major Revision Date: 04/23/98 54LS74-X REV 1A0 DUAL POSITIVE EDGE-TRIGGERED D FLIP-FLOPS with PRESET, CLEAR and COMPLEMENTARY OUTPUTS General Description The 'LS74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary


    Original     		PDF MNDM54LS74-X M0001611

    Untitled

    Abstract: No abstract text available
    Text: ^ M O T O R O L A M ilitary 5 4 LS7 4 A D u a l D -Type Flip-Flop W ith C le a r and P reset ELECTRICALLY TESTED PER: MIL-M-38510/30102 The 54LS74A dual e dg e -trig ge re d flip -flo p u tilizes S chottky TTL c irc u i­ try to produce high-speed D -type flip -flo p s . Each flip -flo p has in d iv id u a l


    OCR Scan     		PDF MIL-M-38510/30102 54LS74A

    DM74LS74AN

    Abstract: No abstract text available
    Text: LS74A National ÉSA Semiconductor 54LS74/54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the


    OCR Scan     		PDF 54LS74/DM54LS74A/DM74LS74A DM74LS74AN

    54LS74

    Abstract: No abstract text available
    Text: LS74A National Semiconductor 54LS74/54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the


    OCR Scan     		PDF LS74A 54LS74/DM54LS74A/DM74LS74A 54LS74

    DM74LS74AN

    Abstract: 54LS74 54LS74DMQB 54LS74FMQB 54LS74LMQB DM54LS74AJ DM54LS74AW DM74LS74AM E20A 074d
    Text: June 1989 54LS74/54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-trig­ gered D flip-flops with complementary outputs. The informa­


    OCR Scan     		PDF 54LS74/DM54LS74A/DM74LS74A DM74LS74AN 54LS74 54LS74DMQB 54LS74FMQB 54LS74LMQB DM54LS74AJ DM54LS74AW DM74LS74AM E20A 074d

    Untitled

    Abstract: No abstract text available
    Text: & June 1989 54LS74/54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-trig­ gered D flip-flops with complementary outputs. The informa­


    OCR Scan     		PDF 54LS74/DM54LS74A/DM74LS74A

    54LS74A

    Abstract: No abstract text available
    Text: M ilita ry 54L S 74A MOTOROLA Dual D-iype Flip-Flop W ith C le ar and P reset ELECTRICALLY TESTED PER: MIL-M-38510/30102 M The 54LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high-speed D-type flip-flops. Each flip-flop has


    OCR Scan     		PDF MIL-M-38510/30102 54LS74A JM38510/30102BXA

    Untitled

    Abstract: No abstract text available
    Text: M MOTOROLA M ilitary 54LS74A Dual D -iype Flip-Flop With Clear and Preset ELECTRICALLY TESTED PER: MIL-M-38510/30102 H T h e 54LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high-speed D-type flip-flops. Each flip-flop has


    OCR Scan     		PDF 54LS74A MIL-M-38510/30102 54LS74A JM38510/30102BXA

    54LS74A

    Abstract: Di801 max5539 54S74
    Text: Signetics 54LS74A, 54S74 Flip-Flops Dual D-Type Flip-Flops Product Specification Military Logic Products DESCRIPTION The 54LS7 4 A , 5 4 S 7 4 is a dual positive edge-triggered D-type flip-flop featuring individual Data, Clock, Set and R eset in­ puts; also com plem entary Q and O out­


    OCR Scan     		PDF 54LS74A, 54S74 54LS7 54LSXXX 54SXXX 28Oil 500ns 500ns 54LS74A Di801 max5539 54S74

    74ls74a ic

    Abstract: SN54L74
    Text: TYPES SN5474, SN54H74, SN54L74, 54LS74A, SN54S74, SN7474, SN74H74, SN74LS74A, SN74S74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR R E V IS E D D E C E M B E R 1983 Package Options Include Both Plástic and Ceram ic Chip Carriers in Addition to Plastic


    OCR Scan     		PDF SN5474, SN54H74, SN54L74, SN54LS74A, SN54S74, SN7474, SN74H74, SN74LS74A, SN74S74 74ls74a ic SN54L74

    74s188 programming

    Abstract: 74S471 N82S06 74S470 dip18 package str 52100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 74S472 PROM PROGRAMMING 8080a 74S287 programming instructions
    Text: The E ngineering Staff of TEXAS INSTRUMENTS INCORPORATED Semiconductor Memory Data Book y for \ T exas In Design Engineers s t r u m e n t s >le of Contents • Alphanumeric Index • GENERAL INFORMATION Selection Guides • Glossary INTERCHANGEABILITY GUIDE


    OCR Scan     		PDF 38510/MACH MIL-M-38510 74s188 programming 74S471 N82S06 74S470 dip18 package str 52100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 74S472 PROM PROGRAMMING 8080a 74S287 programming instructions

    74LS115

    Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
    Text: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25


    OCR Scan     		PDF

    74ls169 motorola

    Abstract: 8 decade counter
    Text: g MOTOROLA SN54LS/74LS168 SN54LS/74LS169 D E S C R IP T IO N — Th eS N 54LS /7 4LS 16 8and S N 5 4LS /74 LS 169 are fully synchronous 4-stage u p /d o w n counters featuring a preset capability for programmable operation, carry lookahead for easy cas­


    OCR Scan     		PDF /74LS SN54LS/74LS168 SN54LS/74LS169 74ls169 motorola 8 decade counter

    SN74ALS123

    Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
    Text: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS


    OCR Scan     		PDF MIL-M-38510 SN74ALS123 SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138

    dm8130

    Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
    Text: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408


    OCR Scan     		PDF 54H00 54L00 54LS00 54H01 54L01 54LS01 54L02 54LS02 54L03 54LS03 dm8130 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76

    DM74367

    Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
    Text: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,


    OCR Scan     		PDF

    54LS641

    Abstract: CD Octal D-type flip-flop 74LS00 QUAD 2-INPUT NAND GATE 54LS642 54LS154 74LS00 quad TTL nand gate 74ls00 NAND gate SchottkyBarrierDiode 54LS92 54LS623
    Text: MAXIMUM RATINGS Supply Voltage - Vcc T h e S e rie s 5 4 L S /7 4 L S Schottky TTL family features both Schottky-barrier-diode inputs and em itte r inputs and u tilizes full Schottky-barrier-diode clamping to achieve speeds com parable to Series 54/74 at one-fifth of the


    OCR Scan     		PDF 54LS00 74LS00 24-LEAD 20-LEAD 54LS390/E 54LS393/C 54LS395A/E 54LS445/E 54LS490/E 54LS533/R 54LS641 CD Octal D-type flip-flop 74LS00 QUAD 2-INPUT NAND GATE 54LS642 54LS154 74LS00 quad TTL nand gate 74ls00 NAND gate SchottkyBarrierDiode 54LS92 54LS623

    bipolar PROM

    Abstract: plhs18p8 S4LS04 82HS641 PLHS18 54175 82s137a 82S191 68172 54F04
    Text: Signetics I Alphanumeric I Index Military Products H LM119 LM124 LM139 Vol. 1 17 Dual Voltage Comparator Vol.2 22 26 26 Low Power Quad Op Amp LM139A Qual Voltage Comparator Qual Voltage Comparator PLC18V8Z Zero Standby Power Universal PAL -Type Device PLC415


    OCR Scan     		PDF LM119 LM124 LM139 LM139A PLC18V8Z PLC415 PLHS18P8A PLHS473 PLHS501 PLS105 bipolar PROM plhs18p8 S4LS04 82HS641 PLHS18 54175 82s137a 82S191 68172 54F04

    7474PC

    Abstract: 74LS74PC 74h74p 74LS74DC 74ls74D 7474 truth table 74H74D 7474 D flip-flop 7474 pin out diagram 74H74DC
    Text: 74 CONNECTIO N DIAGRAMS PINOUT A 54/7474 < 2 y / 6 ‘ V/S4H/74H74 û / / ^S4S/74S74 0 / / 5 3 s 54L S /74L S 74 { / / i ; = DUAL D-TYPE POSITIVE EDGETRIGGERED FLIP-FLOP D DESCRIPTION — T h e '74 devices are dual D-type flip -flop s with Direct Clear and Set inputs and com plem entary Q, Q outputs. Inform ation at the input is


    OCR Scan     		PDF /S4H/74H74 4S/74S74 -54LS/74LS74r//c 64/74H 54/74S 54/74LS 7474PC 74LS74PC 74h74p 74LS74DC 74ls74D 7474 truth table 74H74D 7474 D flip-flop 7474 pin out diagram 74H74DC

    SN74574

    Abstract: SN7457 sn7474 SN5474 SN54LS74A SN54S74 SN74 SN74LS74A SN74S74
    Text: SN5474, 54LS74A, SN54S74, SN7474, SN74LS74A, SN74S74 SDLS119 DUAL 0-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR DECEMBER 1 9 B 3 - Package Options Include Plastic "Small Outline" Packages. Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic


    OCR Scan     		PDF SDLS119 SN5474, SN54LS74A, SN54S74, SN7474, SN74LS74A, SN74S74 SN74574 SN7457 sn7474 SN5474 SN54LS74A SN54S74 SN74 SN74LS74A