LH5492
Abstract: 32-PIN
Text: LH5492 FEATURES • Fast Cycle Times: 25/30/35 ns Frequency: 40/33/28.5 MHz • Parallel Data In; Parallel Data Out • Two Read Enable Inputs and Two Write Enable Inputs, Sampled on Rising Edge of the Appropriate Clock • Fast-Fall-Through Time Internal Architecture Based
|
Original
|
PDF
|
LH5492
32PLCC-1
32-pin,
450-mil
32-pin
PLCC32-P-R450-PED)
LH5492U-25
5492MD
LH5492
|
Untitled
Abstract: No abstract text available
Text: LH5492 4 K x 9 Clocked FIFO FEATURES status output signals are synchronized to these clocks, to simplify system design. The input and output ports oper ate altogether independently of each other, except when the FIFO becomes either totally full or else totally empty.
|
OCR Scan
|
PDF
|
LH5492
32-Pin
PLCC32-P-R450-PED)
32-pin,
450-mil
LH5492U-25
|
lh5492
Abstract: No abstract text available
Text: LH5492-/ 4K x 9 Clocked FIFO simplify system design. The input and output ports oper ate altogether independently of each other, except when the FIFO becomes either absolutely full or else absolutely empty. FEATURES • Fast Cycle Times: 25/35/50 ns Frequency: 40/28.5/20 MHz
|
OCR Scan
|
PDF
|
LH5492-/
32-Pin
Oct91
LH5492
LHE492
PLCC32-P-S450)
LH5492U-25
lh5492
|
Untitled
Abstract: No abstract text available
Text: LH5492 FEATURES • Fast Cycle Times: 25/30/35 ns Frequency: 40/33/28.5 MHz • Parallel Data In; Parallel Data Out • Two Read Enable Inputs and Two Write Enable Inputs, Sampled on Rising Edge of the Appropriate Clock • Fast-Fall-Through Time Internal Architecture Based
|
OCR Scan
|
PDF
|
LH5492
32-Pin
PLCC32-P-R450)
LH5492U-25
5492MD
|
Untitled
Abstract: No abstract text available
Text: LH5492 FEATURES • Fast Cycle Times: 25/30/35 ns Frequency: 40/33/28.5 MHz • Parallel Data In; Parallel Data Out • Two Read Enable Inputs and Two Write Enable Inputs, Sampled on Rising Edge of the Appropriate Clock • Fast-Fall-Through Time Internal Architecture Based
|
OCR Scan
|
PDF
|
LH5492
32-Pin
LH5492
PLCC32-P-R450-PED)
LH5492U-25
5492MD
|