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    CY7C1461V25

    Abstract: CY7C1463V25 CY7C1465V25
    Text: CY7C1461V25 CY7C1463V25 CY7C1465V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles •Supports 133-MHz bus operations •1M x 36/2M × 18/512K × 72 common I/O


    Original     		PDF CY7C1461V25 CY7C1463V25 CY7C1465V25 36/2M 18/512K 133-MHz 36/2M 18/512K 150-MHz CY7C1461V25 CY7C1463V25 CY7C1465V25

    Untitled

    Abstract: No abstract text available
    Text: CY7C1480V33 CY7C1482V33 CY7C1486V33 ADVANCE INFORMATION 2M x 36/4M x 18/1M x 72 Pipelined SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 300, 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate


    Original     		PDF CY7C1480V33 CY7C1482V33 CY7C1486V33 36/4M 18/1M CY7C1480V33/CY7C1482V33/CY7C1482V33

    CY7C1440V33

    Abstract: No abstract text available
    Text: CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate Fast access time: 2.7, 3.0 and 3.5 ns


    Original     		PDF CY7C1440V33 CY7C1442V33 CY7C1446V33 36/2M 18/512K CY7C1440V33/CY7C1442V33/CY7C1446V33 CY7C1440V33

    cy7c1470v25

    Abstract: No abstract text available
    Text: CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBLTM Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™


    Original     		PDF CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit CY7C1470V25/CY7C1472V25/CY7C1474V25

    Untitled

    Abstract: No abstract text available
    Text: CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Functional Description Features The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are


    Original     		PDF CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit CY7C1470V33, CY7C1472V33, CY7C1474V33

    Untitled

    Abstract: No abstract text available
    Text: CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBLTM Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™


    Original     		PDF CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 200-MHz CY7C1470V25/CY7C1472V25/CY7C1474V25

    Untitled

    Abstract: No abstract text available
    Text: CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT


    Original     		PDF CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit CY7C1470V33, CY7C1472V33, CY7C1474V33

    250ac to 30 v ac

    Abstract: CY7C1462V25 CY7C1464V25 CY7C1460V25
    Text: CY7C1460V25 CY7C1462V25 CY7C1464V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 250, 200, and 167 MHz • Fast access time: 2.7, 3.0 and 3.5 ns


    Original     		PDF CY7C1460V25 CY7C1462V25 CY7C1464V25 36/2M 18/512K CY7C1460V25 CY7C1462V25 250ac to 30 v ac CY7C1464V25

    CY7C1443V33

    Abstract: CY7C1441V33
    Text: CY7C1441V33 CY7C1443V33 CY7C1447V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-through SRAM Features • Supports 133-MHz bus operations • 1M x 36/2M x 18/512K x 72 common I/O • Fast clock-to-output times — 6.5 ns for 133-MHz device — 7.5 ns (for 117-MHz device)


    Original     		PDF CY7C1441V33 CY7C1443V33 CY7C1447V33 36/2M 18/512K 133-MHz 117-MHz CY7C1443V33 CY7C1441V33

    cy7c147bv-25

    Abstract: No abstract text available
    Text: CY7C1471V25 72-Mbit 2 M x 36 Flow-Through SRAM with NoBL Architecture 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles


    Original     		PDF CY7C1471V25 72-Mbit CY7C1471V25 cy7c147bv-25

    Untitled

    Abstract: No abstract text available
    Text: CY7C1441AV33 36-Mbit 1 M x 36 Flow-Through SRAM 36-Mbit (1 M × 36) Flow-Through SRAM Features Functional Description • Supports 133-MHz bus operations ■ 1 M × 36 common I/O ■ 3.3 V core power supply ■ 2.5 V or 3.3 V I/O power supply ■ Fast clock-to-output times


    Original     		PDF CY7C1441AV33 36-Mbit CY7C1441AV33 133-MHz

    cy7c1470v25

    Abstract: No abstract text available
    Text: CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBLTM Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™


    Original     		PDF CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit CY7C1470V25/CY7C1472V25/CY7C1474V25

    Diagrams

    Abstract: 5185143 BG-272 mold cap BG256 BG352 BG-209 Package Diagrams 14X22
    Text: Package Diagrams Ball Grid Array Packages 119-Lead PBGA 14 x 22 x 2.4 mm BG119 51-85115-*A 1 Package Diagrams 209-Lead PBGA (14 x 22 x 2.20 mm) BG209 51-85143-*A 2 Package Diagrams 256-Lead PBGA (27 x 27 x 2.33 mm) BG256 51-85097-*A 3 Package Diagrams 272-Lead Ball Grid Array (27 x 27 x 2.33 mm) BG272


    Original     		PDF 119-Lead BG119 209-Lead BG209 256-Lead BG256 272-Lead BG272 388-Lead BG352 Diagrams 5185143 BG-272 mold cap BG256 BG352 BG-209 Package Diagrams 14X22

    CY7C1441V33

    Abstract: CY7C1443V33
    Text: CY7C1441V33 CY7C1443V33 CY7C1447V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-Thru SRAM Features inputs include all addresses, all data inputs, addresspipelining Chip Enable CE , Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd,


    Original     		PDF CY7C1441V33 CY7C1443V33 CY7C1447V33 36/2M 18/512K 133-MHz 36/2M 18/512K 150-MHz CY7C1441V33 CY7C1443V33

    Untitled

    Abstract: No abstract text available
    Text: CY7C1471V33 72-Mbit 2 M x 36 Flow-Through SRAM with NoBL Architecture 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture Functional Description Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles


    Original     		PDF CY7C1471V33 72-Mbit 133-MHz

    cy7c1470v25

    Abstract: No abstract text available
    Text: CY7C1470V25 CY7C1472V25 CY7C1474V25 ADVANCE INFORMATION 2M x 36/4M x 18/1M x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency™, no dead cycles between Write and Read cycles • Fast clock speed: 300, 250, 200, and 167 MHz • Fast access time: 2.2, 2.4, 3.0, and 3.4 ns


    Original     		PDF CY7C1470V25 CY7C1472V25 CY7C1474V25 36/4M 18/1M CY7C1470V25/CY7C1472V25/CY7C1474V25

    Untitled

    Abstract: No abstract text available
    Text: CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT


    Original     		PDF CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit CY7C1470V33, CY7C1472V33, CY7C1474V33

    CY7C1470V25

    Abstract: CY7C1472V25 CY7C1474V25
    Text: CY7C1470V25 CY7C1472V25 CY7C1474V25 PRELIMINARY 2M x 36/4M x 18/1M x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency™, no dead cycles between Write and Read cycles • Fast clock speed: 250, 200, and 167 MHz • Fast access time: 2.6, 3.0, and 3.4 ns


    Original     		PDF CY7C1470V25 CY7C1472V25 CY7C1474V25 36/4M 18/1M suspe7C1470V25 CY7C1470V25/CY7C1472V25/CY7C1474V25 CY7C1470V25 CY7C1472V25 CY7C1474V25

    CY7C1460V33

    Abstract: CY7C1462V33
    Text: CY7C1460V33 CY7C1462V33 CY7C1464V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 250, 200, and 167 MHz • Fast access time: 2.7, 3.0 and 3.5 ns


    Original     		PDF CY7C1460V33 CY7C1462V33 CY7C1464V33 36/2M 18/512K oCY7C1460V33 CY7C1460V33/CY7C1462V33/CY7C1464V33 CY7C1460V33 CY7C1462V33

    CY7C1461V25

    Abstract: CY7C1463V25 CY7C1465V25
    Text: CY7C1461V25 CY7C1463V25 CY7C1465V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 F/T SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles •Supports 133-MHz bus operations •1M x 36/2M x18/512K x 72 common I/O


    Original     		PDF CY7C1461V25 CY7C1463V25 CY7C1465V25 36/2M 18/512K 133-MHz x18/512K 117-MHz CY7C1461V25 CY7C1463V25 CY7C1465V25

    tdb 117

    Abstract: CY7C1471V33 CY7C1473V33 CY7C1475V33
    Text: CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY 2M x 36/4M x 18/1M x 72 Flow-through SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Supports 133-MHz bus operations • 2M x 36/4M × 18/1M × 72 common I/O


    Original     		PDF CY7C1471V33 CY7C1473V33 CY7C1475V33 36/4M 18/1M 133-MHz 36/4M 18/1M 150-MHz tdb 117 CY7C1471V33 CY7C1473V33 CY7C1475V33

    Untitled

    Abstract: No abstract text available
    Text: CY7C1441AV33 36-Mbit 1 M x 36 Flow-Through SRAM 36-Mbit (1 M × 36) Flow-Through SRAM Features Functional Description • Supports 133-MHz bus operations ■ 1 M × 36 common I/O ■ 3.3 V core power supply ■ 2.5 V or 3.3 V I/O power supply ■ Fast clock-to-output times


    Original     		PDF CY7C1441AV33 36-Mbit CY7C1441AV33 133-MHz

    CY7C1481V33

    Abstract: CY7C1483V33 CY7C1487V33
    Text: CY7C1481V33 CY7C1483V33 CY7C1487V33 PRELIMINARY Logic Block Diagrams CY7C1481V33 – 2M x 36 MODE A[1;0] 2 BURST Q0 CE COUNTER Q1 CLR CLK ADV ADSC ADSP Q A[20:0] 21 GW 19 DQd, DPd BYTEWRITE REGISTERS DQc, DPc BYTEWRITE REGISTERS Q D DQb, DPb BYTEWRITE REGISTERS


    Original     		PDF CY7C1481V33 CY7C1483V33 CY7C1487V33 CY7C1481V33/CY7C1483V33/CY7C1487V33 36/4M CY7C1481V33 CY7C1483V33 CY7C1487V33

    Untitled

    Abstract: No abstract text available
    Text: CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBLTM Architecture Functional Description Features • Pin-compatible and functionally equivalent to ZBT™


    Original     		PDF CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 200-MHz