MA1019
Abstract: No abstract text available
Text: October 2001 Advance Information AS7C1025A AS7C31025A 5V/3.3V 128K X 8 CMOS SRAM Revolutionary pinout Features • • • • • AS7C1025A (5V version) AS7C31025A (3.3V version) Industrial and commercial temperatures Organization: 131,072 x 8 bits High speed
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AS7C1025A
AS7C31025A
AS7C1025A
AS7C1025A)
AS7C31025A)
32-pin,
MA1019
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Untitled
Abstract: No abstract text available
Text: $SULO##5333 $6:&4357 $6:&64357 8926169#45;.ð;#&026#65$0#+ YROXWLRQDU\#3LQRXW, HDWXUHV • AS7C1024 (5V version) • AS7C31024 (3.3V version) • Industrial and commercial temperatures • Organization: 131,072 words x 8 bits • High speed - 10/12/15/20 ns address access time
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AS7C1024
AS7C31024
AS7C1024)
AS7C31024)
32-pin
20007C31024-15JI
AS7C1024-15TC
AS7C1024-15TI
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AS7C31024-12TC
Abstract: AS7C1024-15TJC
Text: $6& $6& .ð&02665$0 &RPPRQ,2 IDPLO\ HDWXUHV • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages - 300 mil PDIP and SOJ Socket compatible with 7C512 64Kx8) - 400 mil SOJ - 8mm × 20mm TSOP • ESD protection ≥ 2000 volts
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32-pin
7C512
pS7C31024-15JI
AS7C31024L-15JC
AS7C1024-15TC
AS7C1024L-15TC
AS7C31024-15TC
AS7C31024L-15TC
AS7C1024-20TJC
AS7C1024L-20TJC
AS7C31024-12TC
AS7C1024-15TJC
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Untitled
Abstract: No abstract text available
Text: March 2001 Advance Information AS7C1025A AS7C31025A 5V/3.3V 128K X 8 CMOS SRAM Revolutionary pinout • • • • • • Latest 6T 0.25u CMOS technology 2.0V data retention Easy memory expansion with CE, OE inputs Center power and ground TTL/LVTTL-compatible, three-state I/O
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AS7C1025A
AS7C31025A
AS7C1025A
AS7C1025A)
AS7C31025A)
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TC528257
Abstract: n724
Text: TOSHIBA SILICON GATE CMOS TC528257 t a r g e t s p e c 262,144WORDS X 8BITS MULTIPORT DRAM DESCRIPTION The TC528257 is a 2M bit CM OS multiport m em ory equipped with a 262,144-w ords by 8 -bits dynam ic random access m em ory RAM port and a 512-words by 8 -bits static serial access m emory (SA M ) port. The
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TC528257
144WORDS
TC528257
144-w
512-words
TC528257J/SZ/nVTR1017240
TC528257J/SZ/FT/TR-70
TC528257J/SZ/FT/TR-80
n724
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SF229
Abstract: toshiba s105
Text: TOSHIBA TC528257 t a r g e t s il ic o n g a t e c m o s s p e c 262,144WORDS X 8BITS MULTIPORT DRAM DESCRIPTION T h e T C 5 2 8 2 5 7 is a 2M b it C M O S m u ltip o rt m e m o ry eq u ip p e d w ith a 2 6 2 ,1 4 4 -w o rd s b y ra n d o m a ccess m e m o ry R A M p o rt a n d a 5 1 2 -w o rd s by
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TC528257
144WORDS
SF229
toshiba s105
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TC518129
Abstract: de interlace
Text: TOSHIBA TC518129AP/ASP/AF/AFW-80/10/12 TC518129APL/ASPL/AFL/AFWL30/10/12 TC518129AFTLS0/10/12 SILICON GATE CMOS 131,072 WORD x 8 BIT CMOS PSEUDO STATIC RAM Description The T C 5 1 8 1 2 9 A is a 1M bit high speed C M O S p se udo static R AM organized as 131,07 2 w o rd s by 8 bits. The TC 5 18 1 29A utilizes
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TC518129AP/ASP/AF/AFW-80/10/12
TC518129APL/ASPL/AFL/AFWL30/10/12
TC518129AFTLS0/10/12
TC518129APL/ASPL/AFL/AFWL/AFTL-80/10/12
AO-A16
TC518129
de interlace
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518128
Abstract: 518128apl TC518128
Text: TOSHIBA TC518128APL/AFL/AFWL-80LV/10LV/12LV TC518128AFTLS0LV/10LV/12LV SILICON GATE CMOS 131,072 WORD x 8 BIT CMOS PSEUDO STATIC RAM Description T h e T C 5 1 8 1 2 8 A -L V is a 1M bit high speed C M O S p se udo static R AM organized as 131,07 2 w o rd s b y 8 bits. The T C 5 1 8 1 2 8 A -L V
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TC518128APL/AFL/AFWL-80LV/10LV/12LV
TC518128AFTLS0LV/10LV/12LV
518128APLyAFL/AFW
L/AFTL-80LV/1
OLV/12LV
518128APL/AFL/AFW
L/AFTL-80LV/1O
LV/12LV
2SA1015
518128
518128apl
TC518128
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TC518129AFwl
Abstract: No abstract text available
Text: TOSHIBA TC518129APL/AFL/AFWL-80LV/lOLV/12LV TC518129AFTL80LV/lOLV/12LV SILICON GATE CM O S 131,072 W ORD x 8 BIT C M O S PSEUDO STATIC RAM D escription The TC5181 29A-LV is a 1M bit high speed CMOS pseudo static RAM organized as 131,072 words by 8 bits. The TC518129A-LV
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TC518129APL/AFL/AFWL-80LV/lOLV/12LV
TC518129AFTL80LV/lOLV/12LV
TC5181
TC518129A-LV
D-112
TC518129APL/AFL/AFWL/AFTL-80LV/1OLV/12LV
D-113
TC518129APL/AFL/AFWL/AFTL-80LV/1
TC518129AFwl
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Untitled
Abstract: No abstract text available
Text: High Performance 128Kx8 C M O S SRAM p i AS7C1024 AS7C1024L 128Kx8 CM O S S RAM Common I/O FEATURES • Organization: 131,072 words x 8 bits • Equal access and cycle times • High speed • Easy memory expansion with CE1, CE2, OE inputs - 10/12/15/20/25/35 ns address access time
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128Kx8
AS7C1024
AS7C1024L
128Kx8
32-pin
7C256
7C512
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Untitled
Abstract: No abstract text available
Text: March 1994 PRELIMINARY DATA SHEET_ M 65608 128 K x 8 ULTIMATE CMOS SRAM FEATURES . ACCESS TIME: COMMERCIAL: 25/30/35/45 ns INDUSTRIAL AND MILITARY: 25 * /30/35/45 ns . VERY LOW POWER CONSUMPTION ACTIVE: 250 mW (typ) STANDBY: 1 pW (typ)
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Untitled
Abstract: No abstract text available
Text: TC518129CPL/CFWL/CFIL-70/80/10 TC518129CPL/CFWL/CFIL-70L/80L/10L SILICON GATE CMOS P R E L IM IN A R Y 131,072 WORD x 8 BIT CMOS PSEUDO STATIC RAM D e s c rip tio n The T C 5 1 8 1 2 9 C is a 1 M bit high speed C M O S pse udo static RAM organized as 131,072 w o rd s by 8 bits. T h e T C 5 1 8 1 2 9 C utilizes
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TC518129CPL/CFWL/CFIL-70/80/10
TC518129CPL/CFWL/CFIL-70L/80L/10L
Q02bbl3
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Untitled
Abstract: No abstract text available
Text: TOSHIBA TC528257 t a r g e t s il ic o n g a t e c m o s 262,144WORDS X 8BITS MULTIPORT DRAM DESCRIPTION T h e T C 5 2 8 2 5 7 is a 2 M b it C M O S m u ltip o rt m e m o ry e q u ip p e d w ith a 2 6 2 ,1 4 4 -w o rd s b y ra n d o m access m e m o ry R A M p o rt an d a 5 1 2 -w o rd s b y
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TC528257
144WORDS
C-231
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st d83
Abstract: TC518128C d83 st
Text: TOSHIBA TC518128CPL/CSPL/CFL/CFWL/CFIL-70/80/10 TC518128CPL/CSPL/CFL/CFWL/CFIL-70L/80L/10L PRELIMINARY SILICON GATE CMOS 131,072 WORD x 8 BIT CMOS PSEUDO STATIC RAM Description T h e T C 5 1 8 1 2 8 C is a 1M bit high speed C M O S pse udo static RAM organized as 131,07 2 w o rd s by 8 bits. The TC 5 18 1 28C utilizes
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TC518128CPL/CSPL/CFL/CFWL/CFIL-70/80/10
C518128CPL/CSPL/CFL/CFWL/CFIL-70L/80L/10L
TC518128CPL/CSPUCFL/CFWL/CFTL-70/80/10
CS18128CPL/CSPL/CFL/CFWL/CFTL-70L/80L/1OL
st d83
TC518128C
d83 st
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Untitled
Abstract: No abstract text available
Text: <ä v GM76C8128A/AL/ALL GoldStar 131,072 WORDS x 8 BIT CMOS STATIC RAM GOLDSTAR ELECTRON CO., LTD. Pin Configuration Description The GM76C8128A/AL/ALL is a 1,084,576 bits stat ic random access memory organized as 131,072 words by 8 bits. Using a 0.8um advanced CMOS
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GM76C8128A/AL/ALL
GM76C8128A/AL/ALL
70/85/100ns.
32-pin
600mil)
402A7S7
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Untitled
Abstract: No abstract text available
Text: KM658128/L/L-L/LD/LD-L Pseudo SRAM SAMSUNG ELECTRONICS INC 42E D BB 7 ^ 4 1 4 2 12 8K X 8 Bit CMOS Pseudo Static RAM . QQiaflSS T f FEATURES GENERAL DESCRIPTION • Fast Access Time: — 5 1 Access Time . 80,100,120ns Max. — Cycle Time . Random Read/Write Cycle
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KM658128/L/L-L/LD/LD-L
120ns
190ns
200mW
KM658128LD/
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tc528257
Abstract: W640 SFC39 DIN 41162
Text: TOSHIBA SILICON GATE CMOS TC528257 t a r g e t s p e c 262,144WORDS X 8BITS MULTIPORT DRAM DESCRIPTION The TC528257 is a 2M bit CM OS m ultiport m em ory equipped with a 262,144-words by 8 -bits dynam ic random access mem ory RAM port and a 512-words by 8 -bits static serial access memory (SA M ) port. The
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TC528257
144WORDS
TC528257
144-words
512-words
-84UUHEB-fl-B
TC528257J/SZ/FT/TRâ
TC528257J/SZ/FT/TR-70
W640
SFC39
DIN 41162
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SOJ32-P-400-1
Abstract: TC55V8128BJ
Text: TOSHIBA TC55V8128BJI/BFTI-10,-12 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 131,072-WORD BY 8-BIT CMOS STATIC RAM DESCRIPTION The TC55V8128BJI/BFTI is a 1,048,576 bits high speed static random access memory organized as 131,072 words by 8 bits using CMOS technology, and operated from a single 3.3V supply. Toshiba’s
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TC55V8128BJI/BFTI-10
072-WORD
TC55V8128BJI/BFTI
SOJ32-P-4QO-1
21-38MAX
32-P-400-0
SOJ32-P-400-1
TC55V8128BJ
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SOJ32-P-400-1
Abstract: TC55V8128BJ 512X256X8
Text: TOSHIBA TC55V8128BJ/BFT-8 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 131,072-WORD BY 8-BIT CMOS STATIC RAM DESCRIPTION The TC55V8128BJ/BFT is a 1,048,576 bits high speed static random access memory organized as 131,072 words by 8 bits using CMOS technology, and operated from a single 3.3V supply. Toshiba’s
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TC55V8128BJ/BFT-8
072-WORD
TC55V8128BJ/BFT
32-pin
SOJ32-P-4QO-1
38MAX
SOJ32-P-400-1
TC55V8128BJ
512X256X8
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megatron
Abstract: 10N12 Beacon 406 MHz AS7C31024 BJ 919 26A41
Text: High Performance 128Kx8 3.3V CMOS SRAM H J 8 |j ^ AS7C31024 AS7C31024L PRELIMINARY _ Low Voltage 128Kx8 CMOS SRAM Common I/O FEATURES • Organization: 131,072 words x 8 bits • Equal access and cycle times • Single 3.3 ±0.3V power supply
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AS7C31024
128Kx8
AS7C31024L
D3H41!
megatron
10N12
Beacon 406 MHz
AS7C31024
BJ 919
26A41
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7C1025-15
Abstract: 20013 AS7C1025 AS7C31025 ASC310 275mWmax 7C1025
Text: H ig h P erfo rm a n ce 128K x8 CMOS SRAM » A S7C 1 025 A S 7 C 3 102 5 H A 1 2 8 K X 8 CM O S SRAM C o m m o n I / O • T T L - c o m p a tib le , th r e e - s ta te I / O • H ig h s p e e d • 3 2 - p i n JEDEC s ta n d a r d p a c k a g e - 3 0 0 / 4 0 0 m i l SOJ
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AS7C1025
128Kx8
AS7C3102
AS7C31025)
AS7C102S-10JC
AS7C1025-12JC
AS7C1025-15JC
AS7C1025-20JC
AS7C31Ã
7C1025-15
20013
AS7C1025
AS7C31025
ASC310
275mWmax
7C1025
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Untitled
Abstract: No abstract text available
Text: M O S E L V /TE LiC V52C8128 MULTIPORT VIDEO RAM WITH 128K X 8 DRAM AND 256 X 8 SAM 70 80 10 Max. RAS Access Time, tHAC HIGH PERFORMANCE V52C812B 70 ns 80 ns 100 ns Max. CAS Access Time, Ocac ) 20 ns 25 ns 25 ns Max. Column Address Access Time, (t*) 35 ns
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V52C8128
V52C812B
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V52C8128
Abstract: V52C8128-80
Text: MOSEL- VITELIC V52C8128 MULTIPORT VIDEO RAM WITH 128K X 8 DRAM AND 256 X 8 SAM HIGH PERFORMANCE V52C8128 70 PRELIMINARY 80 10 Max. RAS Access Time, tRAc 70 ns 80 ns 100 ns Max. CAS Access Time, (tcAc) 20 ns 25 ns 25 ns Max. Column Address Access Time, ( t ^ )
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V52C8128
V52C8128
V52C8128-80
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km658128
Abstract: 658128 PSEUDO SRAM
Text: KM658128/L/L-L/LD/LD-L Pseudo SRAM 12 8 K X 8 Bit CMOS Pseudo Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Time: — CE Access Time . 80,100,120ns Max. — Cycle Time . Random ReadfWrite Cycle Time . 130,160,190ns (Max.) • Low Power Dissipation . 200mW typ. (Active)
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KM658128/L/L-L/LD/LD-L
120ns
190ns
200mW
KM658128LD/
32-Pin
600mil)
525mil)
450mjl)
km658128
658128
PSEUDO SRAM
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