Untitled
Abstract: No abstract text available
Text: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 450 MHz Clock for High Bandwidth
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CY7C11461KV18,
CY7C11571KV18
CY7C11481KV18,
CY7C11501KV18
18-Mbit
CY7C11571KV18,
CY7C11501KV18
CY7C11461KV18)
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 450 MHz Clock for High Bandwidth
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Original
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CY7C11461KV18,
CY7C11571KV18
CY7C11481KV18,
CY7C11501KV18
18-Mbit
CY7C11571KV18,
CY7C11501KV18
CY7C11461KV18)
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PDF
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3M Touch Systems
Abstract: No abstract text available
Text: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 450 MHz Clock for High Bandwidth
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Original
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CY7C11461KV18,
CY7C11571KV18
CY7C11481KV18,
CY7C11501KV18
18-Mbit
3M Touch Systems
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PDF
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as6c4008a
Abstract: 32-pin 8mm x 13,4mm sTSOP
Text: AS6C4008A 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.12 REVISION HISTORY Revision Rev. 1.12 Description Initial Issue Issue Date May 15, 2012 Alliance Memory, Inc. 551 Taylor Way, Suite #1, San Carlos, CA 94070 Phone: 650-610-6800 AS6C4008A 512K X 8 BIT LOW POWER CMOS SRAM
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AS6C4008A
AS6C4008A
304-bit
36pin
32pin
400mil
32-pin 8mm x 13,4mm sTSOP
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PDF
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AS6C4008
Abstract: as6c4008-55sin AS6C4008-55PCN cmos 4008 AUG09 SRAM 32 pin
Text: AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Access time : 55 ns Low power consumption: Operatingcurrent : 30 mA TYP. Standby current : 4 µA (TYP.) Single 2.7V ~ 5.5V power supply All outputs TTL compatible Fully static operation
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AS6C4008
32-pin
36-ball
AS6C4008
304-bit
as6c4008-55sin
AS6C4008-55PCN
cmos 4008
AUG09
SRAM 32 pin
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PDF
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AS6C4008
Abstract: AS6C4008-55PCN
Text: AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Access time : 55 ns Low power consumption: Operating current : 30 mA TYP. Standby current : 4 µA (TYP.) Single 2.7V ~ 5.5V power supply All outputs TTL compatible Fully static operation
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Original
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AS6C4008
32-pin
36-ball
AS6C4008
304-bit
AS6C4008-55PCN
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PDF
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Untitled
Abstract: No abstract text available
Text: AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Access time : 55 ns Low power consumption: Operating current : 30 mA TYP. Standby current : 4 µA (TYP.) Single 2.7V ~ 5.5V power supply All outputs TTL compatible Fully static operation
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Original
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AS6C4008
32-pin
36-ball
AS6C4008
304-bit
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PDF
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AS6C4008
Abstract: No abstract text available
Text: AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Access time : 55 ns Low power consumption: Operating current : 30 mA TYP. Standby current : 4 µA (TYP.) Single 2.7V ~ 5.5V power supply All outputs TTL compatible Fully static operation
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Original
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AS6C4008
32-pin
36-ball
AS6C4008
304-bit
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PDF
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AS6C4008-55PCN
Abstract: AS6C4008 AS6C4008-55SIN AS6C4008-55TIN AS6C4008-55
Text: January 20072007 February AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 512K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Access time : 55 ns Low power consumption: Operatingcurrent : 30/20mA TYP. Standby current : 4 µA (TYP.) C-version Single 2.7V ~ 5.5V power supply
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Original
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AS6C4008
30/20mA
32-pin
36-ball
44-pin
AS6C4008
304-bit
AS6C4008-55PCN
AS6C4008-55SIN
AS6C4008-55TIN
AS6C4008-55
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PDF
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CS18LV40963CI
Abstract: CS18LV40963D
Text: High Speed Super Low Power SRAM 512k word x 8 bit CS18LV40963 DESCRIPTION The CS18LV40963 is a high performance, high speed, low power CMOS Static Random Access Memory organized as 524,288 words by 8 bits and operates from a wide range of 2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques
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CS18LV40963
CS18LV40963
50/55/70ns
CS18LVrved.
36-ball
2004-March
CS18LV40963CI
CS18LV40963D
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PDF
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AS6C4008
Abstract: AS6C4008-55PCN AS6C4008-55SIN
Text: MARCH 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION The AS6C4008 is a 4,194,304-bit low power CMOS static random access memory organized as 524,288 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology.
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AS6C4008
AS6C4008
304-bit
32-pin
MAR/09,
AS6C4008-55PCN
AS6C4008-55SIN
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PDF
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Untitled
Abstract: No abstract text available
Text: January 2007 February 2007 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 512K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Access time : 55 ns Low power consumption: Operatingcurrent : 30/20mA TYP. Standby current : 4 µA (TYP.) C-version Single 2.7V ~ 5.5V power supply
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AS6C4008
30/20mA
32-pin
32-pin
36-ball
AS6C4008
304-bit
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PDF
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Untitled
Abstract: No abstract text available
Text: LY625128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 FEATURES GENERAL DESCRIPTION Fast access time : 35/55/70ns Low power consumption: Operating current : 35/25/20mA TYP. Standby current : 5µA (TYP.) LL-version Single 4.5V ~ 5.5V power supply
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LY625128
LY625128
304-bit
35/55/70ns
35/25/20mA
32-pin
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PDF
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Untitled
Abstract: No abstract text available
Text: LY62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Description Initial Issue Adding PKG type : 32 P-DIP Revised Test Condition of ISB1/IDR Lyontek Inc. reserves the rights to change the specifications and products without notice.
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LY62L5128
LY62L5128
304-bit
32-pin
36-ball
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PDF
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Untitled
Abstract: No abstract text available
Text: LY625128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.5 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Description Initial Issue Revised ISB1/IDR Revised Test Condition of ICC Added -45ns Spec. Added P-DIP PKG Revised Test Condition of ISB1/IDR
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LY625128
-45ns
LY625128
304-bit
32-pin
36-ball
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PDF
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as6c4008-55PCN
Abstract: as6c4008-55sin as6c4008-55 AS6C4008 as6c4008-55p 55pcn
Text: OCTOBER January 20072007 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 512K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Access time : 55 ns Low power consumption: Operatingcurrent : 30/20mA TYP. Standby current : 4 µA (TYP.) C-version Single 2.7V ~ 5.5V power supply
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Original
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AS6C4008
30/20mA
32-pin
36-ball
AS6C4008
304-bit
as6c4008-55PCN
as6c4008-55sin
as6c4008-55
as6c4008-55p
55pcn
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PDF
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Untitled
Abstract: No abstract text available
Text: LY62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.2 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Description Initial Issue Adding PKG type : 32 P-DIP Revised Test Condition of ISB1/IDR Deleted L Spec. Added SL Spec. Revised VTERM to VT1 and VT2
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Original
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LY62L5128
LY62L5128
304-bit
32-pin
36-ball
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PDF
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Untitled
Abstract: No abstract text available
Text: LY62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.3 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Description Initial Issue Adding PKG type : 32 P-DIP Revised Test Condition of ISB1/IDR Deleted L Spec. Added SL Spec. Revised VTERM to VT1 and VT2
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Original
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LY62L5128
LY62L5128
304-bit
32-pin
36-ball
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PDF
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Untitled
Abstract: No abstract text available
Text: LY62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.0 FEATURES GENERAL DESCRIPTION Fast access time : 45/55/70ns Low power consumption: Operating current : 40/30/20mA TYP. Standby current : 20µA (TYP.) L-version 2µA (TYP.) LL-version Single 2.7V ~ 3.6V power supply
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LY62L5128
LY62L5128
304-bit
45/55/70ns
40/30/20mA
32-pin
36-ball
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PDF
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LY625128SL
Abstract: LY625128 3217b
Text: LY625128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 2.3 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 2.0 Rev. 2.1 Rev. 2.2 Rev. 2.3 Description Initial Issue Revised ISB1/IDR Revised Test Condition of ICC Added -45ns Spec.
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Original
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LY625128
-45ns
-35ns
11/1kage
32-pin
36-ball
44-pin
LY625128SL
LY625128
3217b
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PDF
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LY625128
Abstract: ly625128-70 SRAM 34 pin
Text: LY625128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 2.0 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 2.0 Description Initial Issue Revised ISB1/IDR Revised Test Condition of ICC Added -45ns Spec. Added P-DIP PKG Revised Test Condition of ISB1/IDR
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Original
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LY625128
-45ns
32-pin
36-ball
44-pin
LY625128
ly625128-70
SRAM 34 pin
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PDF
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Untitled
Abstract: No abstract text available
Text: LY62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.4 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Description Initial Issue Adding PKG type : 32 P-DIP Revised Test Condition of ISB1/IDR Deleted L Spec. Added SL Spec. Revised VTERM to VT1 and VT2
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Original
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LY62L5128
32-pin
36-ball
44-pin
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PDF
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Untitled
Abstract: No abstract text available
Text: LY62W5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.11 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 1.6 Rev. 1.7 Rev. 1.8 Rev. 1.9 Rev. 1.10 Rev. 1.11 Description Initial Issue Revised VIH to TTL compatible Revised VIH to 0.7*Vcc
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LY62W5128
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PDF
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LY62L5128
Abstract: No abstract text available
Text: LY62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.8 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 1.6 Rev. 1.7 Rev. 1.8 Description Initial Issue Adding PKG type : 32 P-DIP Revised Test Condition of ISB1/IDR Deleted L Spec.
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Original
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LY62L5128
32-pin
36-ball
44-pin
LY62L5128
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PDF
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