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Text: 44S4020C CMOS SDRAM Revision History Revision ,4 November 1997 •tRDL has changed 10ns to 12ns. •Binning -10 does not meet PC 100 characteristics . So AC parameter/Characteristics have changed to 16M 3rd values. REV. 4 Nov. '97 ELECTRONICS CMOS SDRAM
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KM44S4020C
44S4020C
10/AP
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KM44S4020CTG
Abstract: KM44S4020C
Text: 44S4020C CMOS SDRAM 2M x 4BH x 2 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • • • • The 44S4020C is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 2,097,152 words by 4 bits, fabricated with SAMSUNG'S high performance CMOS technol
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KM44S4020C
KM44S4020C
KM44S4020CTG
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