3D7105
Abstract: No abstract text available
Text: 3D7105 MONOLITHIC 5-TAP FIXED DELAY LINE SERIES 3D7105 d a ta devices,vinc FEATURES PACKAGES IN cn 1 8 ID VDD All-silicon, low-power CMOS 02 7 m 01 cn 2 technology 04 cn 3 6m 03 GND m 4 5 ID 0 5 TTL/CMOS compatible inputs and outputs 3D7105Z Vapor phase, IR and wave
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3D7105
3D7105)
3D7105Z
0C-70C)
14-pin
16-pin
10KI2
3D7105
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PDU14F80
Abstract: No abstract text available
Text: data Programmable Delay Units delay devices; inc. 4 Bit T T L Interfaced S ER IES : PDU-14F Tast Logic Specifications: • Supply currant: Icch = 74 ma. Iccl = 3 0 ma. ■ Minimum pulse-width = ■ Delay variation: M onotonie in one direction. ■ P rogram m ed delay tolerance: 5 % o r 1
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PDU-14F
PDU-14F-4
PDU-14F-5
PDU-14F-6
PDU-14F-8
PDU-14F-10
PDU-14F-12
PDU-14F-15
PDU-14F-20
PDU-14F-25
PDU14F80
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Untitled
Abstract: No abstract text available
Text: H C M O S - Logic delayW devicesYinc. data V2&V igital Delay Units „ SERIES: 10 Outputs 16 pins DIP D D U -7 C _ ; Features: • Completely interfaced for HCMOS application ■ No external components required ■ P.C. board space economy achieved
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DDU-7C-25
DDU-7C-100
DDU-7C-150
DDU-7C-200
DDU-7C-250
DDU-7C-300
DDU-7C-400
DDU-7C-500
443fl2
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Untitled
Abstract: No abstract text available
Text: E F a s f L o g ic Programmable Pulse fip n p ra tn r series U C IIC Id lU l PPG-33F 3 Bit TTLInterfaced Features: • Precise pulse widths ■ 3-BIT address ■ 1 ns to 50 ns incrmental steps ■ Trigger inherent delay T do = 3.5 ns ± 2 ns T do = 5.0 ns ± 2 ns
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PPG-33F
PPG-33F-10
PPG-33F-15
PPG-33F-20
PPG-33F-40
PPG-33F-50
443fl2
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Untitled
Abstract: No abstract text available
Text: 3D710S data MONOLITHIC 5-TAP FIXED DELAY LINE SERIES 3D7105 aevices,inc FEATURES PACKAGES IN VDD 1 8 All-silicon, low-power CMOS 02 2 7 01 technology 04 3 6 03 GND 05 4 5 TTL/CMOS compatible inputs and outputs 3D7105Z Vapor phase, IR and wave SOIC solderable
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3D710S
3D7105)
3D7105Z
0C-70C)
14-pin
16-pin
Eb443flE
00G11Ã
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PPG-33F-1
Abstract: PPG-33F-10 PPG-33F-15 PPG-33F-2 PPG-33F-20 PPG-33F-3 PPG-33F-40 PPG-33F-5 PPG-33F-50
Text: ïF ast Logic Programmable Pulse fip n p ra tn r s er ies : U G II G I d I U I ppg~33F 3 Bit T T L Interfaced Features: • Precise pulse widths ■ 3-BIT address ■ 1 ns to 50 ns incrmental steps ■ Trigger inherent delay T d o = 3.5 ns ± Too = 5.0 ns ±
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PPG-33F-
PPG-33F-1
PPG-33F-2
PPG-33F-3
PPG-33F-5
PPG-33F-10
PPG-33F-15
PPG-33F-20
PPG-33F-40
PPG-33F-50
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MDU-28F
Abstract: F125
Text: IF a s t L o g ic Multiple Digital SERIES: MDU-28F MnlloQE _ , „ . a Delay Dnits • P * DIP T I L Interfaced Features: • ■ ■ ■ ■ ■ Auto-insertable. Low cost. Completely interfaced for TTL. Low profile. Fits standard 8 pins DIP socket.
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MDU-28F-6
MDU-28F-8
MDU-28F-10
MDU-28
MDU-28F
F125
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VPG-40-60
Abstract: VPG-40 VPG-40-100 VPG-40-120 VPG-40-25 VPG-40-30 VPG-40-40 VPG-40-50 VPG-40-50M VPG-40-70
Text: EFasf Lo g ic Variable Pulse Generator SERIES: Continuously Variable T2L Interfaced VPG-40 data delay devices; inc. Features: • ■ ■ ■ ■ ■ Input & output fully TTL interfaced and buffered. Low profile. Commercial & military type. Continuously adjustable.
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VPG-40
VPG-40-50M
VPG-40-25
VPG-40-30
VPG-40-40
VPG-40-50
VPG-40-60
VPG-40-70
VPG-40-80
VPG-40-100
VPG-40
VPG-40-120
VPG-40-50M
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