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    4 BIT PARITY GENERATOR Search Results

    4 BIT PARITY GENERATOR Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    93S48PC Rochester Electronics LLC Parity Generator/Checker Visit Rochester Electronics LLC Buy
    54HC4078AJ/B-ROCV Rochester Electronics 54HC280 - Parity Generator/Checker, CMOS, LCC. Dual Marked (86077012A) Visit Rochester Electronics Buy
    54F280/BCA Rochester Electronics LLC 54F280 - Parity Generator/Checker, 9-Bit - Dual marked (M38510/34901BCA) Visit Rochester Electronics LLC Buy
    54F280/BDA Rochester Electronics LLC 54F280 - Parity Generator/Checker, 9-Bit - Dual marked (M38510/34901BDA) Visit Rochester Electronics LLC Buy
    54F280/B2A Rochester Electronics LLC 54F280 - Parity Generator/Checker, 9-Bit - Dual marked (M38510/34901B2A) Visit Rochester Electronics LLC Buy

    4 BIT PARITY GENERATOR Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    DDR3U

    Abstract: SSTE32882 2yn1 DDR3 rdimm pcb layout SSTE32882KA1 DDR3U-1600 da-15 pinout dba1 DDR3 layout DDR3 pcb layout
    Text: DATASHEET Advanced Information 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation.


    Original     		PDF 28-bit 26-bit 32882KA1 SSTE32882KA1 DDR3U SSTE32882 2yn1 DDR3 rdimm pcb layout SSTE32882KA1 DDR3U-1600 da-15 pinout dba1 DDR3 layout DDR3 pcb layout

    SSTE32882KA1

    Abstract: No abstract text available
    Text: DATASHEET Advanced Information 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation.


    Original     		PDF 28-bit 26-bit 32882KA1 SSTE32882KA1 SSTE32882KA1

    Untitled

    Abstract: No abstract text available
    Text: DATASHEET 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.35V and 1.5V VDD operation. All inputs are 1.35V and 1.5V CMOS compatible, except the


    Original     		PDF 28-bit 26-bit SSTE328n 32882HLB SSTE32882HLB

    XLXX

    Abstract: SSTE32882 dba1 SSTE32882HLB JESD8-11A
    Text: DATASHEET 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.35V and 1.5V VDD operation. All inputs are 1.35V and 1.5V CMOS compatible, except the


    Original     		PDF SSTE32882HLB 28-bit 26-bit SSTE32882Hd 32882HLB SSTE32882HLB XLXX SSTE32882 dba1 JESD8-11A

    Untitled

    Abstract: No abstract text available
    Text: DATASHEET 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description CONFIDENTIAL I DT 7 4 SST U BF3 2 8 6 9 A The IDT74SSTUBF32869A includes a parity checking function. The IDT74SSTUBF32869A accepts a parity bit from the memory controller at its input pin PARIN one or


    Original     		PDF 14-BIT IDT74SSTUBF32869A 199707558G

    cK 7201

    Abstract: SSTE32882 SSTE32882HLB xlxx transistor DA3 307 qbba1 dba1 DDR3 layout DDR3 pcb layout DDR3L
    Text: DATASHEET 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.35V and 1.5V VDD operation. All inputs are 1.35V and 1.5V CMOS compatible, except the


    Original     		PDF 28-bit 26-bit SSTE32882HLB 32882HLB SSTE32882HLB cK 7201 SSTE32882 xlxx transistor DA3 307 qbba1 dba1 DDR3 layout DDR3 pcb layout DDR3L

    SSTE32882KB1

    Abstract: XLXX DDR3U-1600 QAA10 DDR3 rdimm pcb layout DDR3U QAA15
    Text: DATASHEET 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation. All inputs are 1.25,1.35V and 1.5V CMOS compatible, except the


    Original     		PDF 28-bit 26-bit 32882KB1 SSTE32882KB1 SSTE32882KB1 XLXX DDR3U-1600 QAA10 DDR3 rdimm pcb layout DDR3U QAA15

    Untitled

    Abstract: No abstract text available
    Text: DATASHEET 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation. All inputs are 1.25,1.35V and 1.5V CMOS compatible, except the


    Original     		PDF 28-bit 26-bit 32882KB1 SSTE32882KB1

    DDR3U

    Abstract: DDR3U-1866 SLGSSTE32882 top 261 yn JESD79-3 dba1 DDR3L DDR3-2133 RC10 RC11
    Text: SLGSSTE32882 DDR3 Registering Clock Driver with Parity and Quad Chip Selects Features • 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity • Supports high density DDR3 modules • Quad Chip Selects • Supports 1.25V up to DDR3U-1866 , 1.35V (up to DDR3L-1866), and 1.5V (up to DDR3-2133)


    Original     		PDF SLGSSTE32882 28-bit 26-bit DDR3U-1866) DDR3L-1866) DDR3-2133) 176-TFBGA 25hich DDR3U DDR3U-1866 SLGSSTE32882 top 261 yn JESD79-3 dba1 DDR3L DDR3-2133 RC10 RC11

    SLGSSTE32882-A04B

    Abstract: DDR3U SLGSSTE32882 SLGSSTE32882-B04B DDR3L DDR3U-1333 ddr3 RDIMM pinout XLXX JESD79-3 RC10
    Text: SLGSSTE32882 DDR3 Registering Clock Driver with Parity and Quad Chip Selects Features • 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity • Supports high density DDR3 modules • Quad Chip Selects • Supports 1.25V up to DDR3U-1333 , 1.35V (up to DDR3L-1333), and 1.5V (up to DDR3-1600)


    Original     		PDF SLGSSTE32882 28-bit 26-bit DDR3U-1333) DDR3L-1333) DDR3-1600) 176-TFBGA 000-0032882-10g SLGSSTE32882-A04B DDR3U SLGSSTE32882 SLGSSTE32882-B04B DDR3L DDR3U-1333 ddr3 RDIMM pinout XLXX JESD79-3 RC10

    Untitled

    Abstract: No abstract text available
    Text: HITACHI/ L O G IC/ AR RA YS /M EN ^5 74 HC180 HD D Ë | 4 4 ^ 5 0 3 001 0425 O 92D 1 0 4 2 5 # 8-bit O dd/Even Parity G enerator/C hecker This universal, monolithic, 9-bit 8 data bits plus 1 parity bit parity generator/checker features odd/even outputs and


    OCR Scan     		PDF HC180 0D1D315 T-90-20

    g0517

    Abstract: No abstract text available
    Text: NATIONAL SEMICOND {LOGIC* t,l SEMICONDUCTOR 61C 5 1 7 2 4 7- 4 5 - / ? - g g National À jà Semiconductor PRELIM" DM54AS280/DM74ÀS280 9-Bit Parity Generator/Checker General Description These universal, 9-bit parity generators/checkers utilize •


    OCR Scan     		PDF DM54AS280/DM74AS280 DM54AS280/DM74 AS280 bS01122 005172b DM54AS280/ DM74AS280 TU/F/6303-2 AS280s g0517

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11853, 74ACT11853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS T I0 1 77— 0 3 4 7 4 , MARCH 1090 54ACT11853 . - JT PACKAGE 74ACT11853 . DW or NT PACKAGE TOP VIEW • Inputs are TTL-Voltage Compatible • High-Speed Bus Transceivers with Parity Generator/Checker


    OCR Scan     		PDF 54ACT11853, 74ACT11853 500-mA 300-mil ACT11853 TI0177-- D3474,

    Untitled

    Abstract: No abstract text available
    Text: 54AC11833, 74AC11833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS T 10165— D 3448, MARCH 1990 High-Speed Bus Transceivers with Parity Generator/Checker 5 4A C 11 8 33 . . . J T P ACKA G E 7 4 A C 11833 . . . D W OR N T P ACKA G E TO P V IE W Parity-Error Flag Open-Draln Output


    OCR Scan     		PDF 54AC11833, 74AC11833 500-mA 300-mll

    54HC280

    Abstract: No abstract text available
    Text: S N 54H C 280, SN74HC2B0 9 BIT ODDIEVEN PARITY GENERATORSfCHECKERS D 2 6 6 4 , DECEMBER I 9 8 2 -R E V IS E D JUNE 19B9 • Generates Either Odd or Even Parity for Nine Data Lines • Cascadable for n-Bits • Can Be Used to Upgrade Existing Systems Using MSI Parity Circuits


    OCR Scan     		PDF SN74HC2B0 300-mil SN54HC280 SNB4HC280 SN74HC280 54HC280

    Untitled

    Abstract: No abstract text available
    Text: 906ZWV Am2906 Quad Two-Input OC Bus Transceiver with Parity DISTINCTIVE CHARACTERISTICS • • • Internal 4-bit odd parity checker/generator. R eceiver has output latch for pipeline operation. R eceiver outputs sink 12 mA. Quad high-speed LSI bus transceiver.


    OCR Scan     		PDF Am2906 100mA TC000820 5398A 9062UJV 906ZUIV

    4 bit odd parity checker

    Abstract: 0539SA
    Text: 906ZUIV Am2906 Quad Two-Input OC Bus Transceiver with Parity DISTINCTIVE CHARACTERISTICS • • • Internal 4-bit odd parity checker/generator. R eceiver has output latch for pipeline operation. R eceiver outputs sink 12 mA. Quad high-speed LSI bus transceiver.


    OCR Scan     		PDF Am2906 100mA 5398A 0539SA 4 bit odd parity checker 0539SA

    SN74HC180

    Abstract: SN54HC180
    Text: S N 5 4 H C 18 0 , S N 7 4 H C 18 0 9-BIT O D D /EV EN P A R IT Y G EN ER A TO R S /C H EC K ER S D 2 4 8 4 , M A R C H 1 9 8 4 -R E V IS E D SEPTEMBER 1 9 8 7 TOP VIEW g description These universal, monolithic, 9-bit (8 data bits plus 1 parity bit) parity generators/checkers,


    OCR Scan     		PDF SN54HC180, SN74HC180 D2484, 1984-REVISED 300-mil SN54HC1 SN74HC180 SN54HC180

    X20C

    Abstract: No abstract text available
    Text: 54AC 11286, 74AC11286 9-BIT PARITY GENERATORS/CHECKERS WITH BUS DRIVER PARITY I/O PORTS T I0 1 19— D 3165, AUGUST 1988— REVISED MARCH 1990 • Generates Either Odd or Even Parity for Nine Data Lines 5 4 A C 1 1286 . . . J P A C K A G E 7 4 A C 11 2 86 . . . 0 O R N P A C K A G E


    OCR Scan     		PDF 74AC11286 500-mA 300-mil X20C

    PFA 10Z

    Abstract: 54ACT 74ACT11286 D3166 54ACT11286
    Text: 54ACT11286, 74ACT11286 9-BIT PARITY GENERATORS/CHECKERS WITH BUS DRIVER PARITY I/O PORTS TI0124— D3166, AU G U ST 1986— REVISED M AR CH 1990 Inputs are TTL-Voltage Compatible 5 4 A C T 1 1286 . . . J P A C K A G E 74A C T11286 . . . D OR N PACKAGE Generates Either Odd or Even Parity for


    OCR Scan     		PDF 54ACT11286, 74ACT11286 TI0124â D3166, 500-mA 300-mil ACT11286 PFA 10Z 54ACT D3166 54ACT11286

    Untitled

    Abstract: No abstract text available
    Text: SN74ALS280, SN74AS280 9-BIT PARITY GENERATORS/CHECKERS D2661, DECEMBER 1982 - REVISED MAY 1986 Generates Either Odd or Even Parity for Nine Data Lines SN 74A LS280, S N 7 4 A S 2 S 0 . . . D O R N PA CKAG E T O P V IE W Cascadable for n-Bits Parity G [ 1T J Ü D V C C


    OCR Scan     		PDF SN74ALS280, SN74AS280 D2661, 300-mil LS280, SN74AS2S0 25-LINE 27-line

    Parity Generators

    Abstract: SN74 SN74ALS280 SN74AS280 SV10 cs86 I80-S
    Text: SN74ALS280, SN74AS280 9-BIT PARITY GENERATORS/CHECKERS D2661, DECEMBER 1982-R E V IS E D M AY 1986 Generates Either Odd or Even Parity for Nine Data Lines S N 7 4A L S 2 80 , S N 7 4 A S 2 8 0 . . . D O R N PACKAGE TO P V IE W Cascadabie for n-Blts Parity


    OCR Scan     		PDF SN74ALS280, SN74AS280 D2661, 1982-REVISED 300-mil 25-LINE 81-LINE ALS280/ Parity Generators SN74 SN74ALS280 SN74AS280 SV10 cs86 I80-S

    CD40101B

    Abstract: 15-V
    Text: CD40101B Types Features: CMOS 9-Bit Parity Generator/Checker High-Voltage T y p e s 2 0 -V olt Rating T h e R C A -C D 4 01 0 1B is a 9-bit (8 data bits plus 1 parity bit) p arity generator/checker. It may be used to detect errors in data trans­ mission or data retrieval. Odd and even


    OCR Scan     		PDF CD40101B 20-Volt RCA-CD40101B CD40101B 15-V

    C444G

    Abstract: 480T
    Text: fax id: 7012 C Y 5 4 / 7 4 F C T 4 8 0 T Dual 8-Bit Parity Generator/Checker * Two 8-bit parity generator/checkers Featu res * Function, p in o u t and drive co m p a tible with FCT and F logic * FCT-A speed at 7.5 ns max. C o m ’ l FCT-B speed at 5.6 ns max. (C o m ’ l)


    OCR Scan     		PDF