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    370PS Search Results

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    370PS Price and Stock

    Fischer Elektronik GmbH & Co KG BL 16 SMD 113 70 PS

    FOR 0.635 MM AND UP TO 0.85 MM
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    DigiKey BL 16 SMD 113 70 PS Bulk 10,000 10
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    JRH Electronics 370PS024MT2010H6

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    DigiKey 370PS024MT2010H6 Bulk 10 1
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    JRH Electronics 370PS024MT2016H8

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    DigiKey 370PS024MT2016H8 Bulk 5 1
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    Pervasive Displays Inc E2370PS0C1

    3.7" EPD, A-MB, W.ITC, FAST UPDA
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    DigiKey E2370PS0C1 Box 1
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    Glenair Inc 370PS024MT2016H8

    Submersible Backshell with Saddle Clamp 20 Shell Size Straight - Bulk (Alt: 370PS024MT2016H8)
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    Avnet Americas 370PS024MT2016H8 Bulk 3 Weeks 1
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    Mouser Electronics 370PS024MT2016H8
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    Verical 370PS024MT2016H8 500 11
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    370PS024MT2016H8 10 1
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    Newark 370PS024MT2016H8 Bulk 8 1
    • 1 $1472.27
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    Interstate Connecting Components 370PS024MT2016H8
    • 1 $1385.6655
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    Powell Electronics 370PS024MT2016H8 5 1
    • 1 $1677.8
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    370PS Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: DS92LV090A DS92LV090A 9 Channel Bus LVDS Transceiver Literature Number: SNLS025C DS92LV090A 9 Channel Bus LVDS Transceiver General Description Features The DS92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from


    Original     		PDF DS92LV090A DS92LV090A SNLS025C

    PCIe cable pinout

    Abstract: No abstract text available
    Text: PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout Features Description • 6 Differential Channel, 1 to 2 demux that will support 5.0Gbps PCIexpress Gen2 signals on one path, and DP 1.1 signals on the second path


    Original     		PDF PI3PCIE2612-B -35dB PI3PCIE2612-B 56-Contact 56-contact, PD-2024 PI3PCIE2612-BZFE PS8932A PCIe cable pinout

    ABT244

    Abstract: CBT3244 CBT3383 SN74ABT244 SN74CBT16209 SN74CBT16214 SN74CBT16233 SN74CBT3244 SN74CBT6800 relais 5v 10ma
    Text: EB 219 Crossbar Technology CBT Verfasser: Peter Forstner Datum: 18.07.95 Rev.: 1.0 Der vorliegende Bericht behandelt die Familie der CBT-Bausteine (Crossbar Technology). Nach der Vorstellung des inneren Aufbaus dieser Schaltungsfamilie werden DC- und AC-Eigenschaften vorgestellt. Den Abschluß bilden verschiedene Applikationsbeispiele die auf den besonderen Eigenschaften der


    Original     		PDF SN74CBT3244 18-Bit ABT244 CBT3244 CBT3383 SN74ABT244 SN74CBT16209 SN74CBT16214 SN74CBT16233 SN74CBT6800 relais 5v 10ma

    AN-808

    Abstract: AN-971 AN-977 DS92LV090A DS92LV090ATVEH
    Text: DS92LV090A 9 Channel Bus LVDS Transceiver General Description Features The DS92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading,


    Original     		PDF DS92LV090A DS92LV090A AN-808 AN-971 AN-977 DS92LV090ATVEH

    AN1108

    Abstract: AN-808 AN-903 AN918 DS92LV090 DS92LV090A DS92LV090ATVEH
    Text: ご注意：この日本語データシートは参考資料として提供しており内容が最新でない 場合があります。製品のご検討およびご採用に際しては、必ず最新の英文デー タシートをご確認ください。


    Original     		PDF DS92LV090A 100mV DS100111 nat2000 AN918; AN1108 DS92LV090A 64-Lead DS92LV090ATVEH AN1108 AN-808 AN-903 AN918 DS92LV090 DS92LV090ATVEH

    ICS853052

    Abstract: ICS853052AG ICS853052AGT MC100EP58 MO-187
    Text: PRELIMINARY Integrated Circuit Systems, Inc. ICS853052 DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS853052 is a Dual LVCMOS / LVTTL-toDifferential 2.5V, 3.3V, 5V LVPECL Multiplexer HiPerClockS


    Original     		PDF ICS853052 ICS853052 853052AG ICS853052AG ICS853052AGT MC100EP58 MO-187

    display 40 pin connector pinout

    Abstract: No abstract text available
    Text: PI3PCIE2612-A High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout Features Description • 6 Differential Channel, 1 to 2 demux that will support 5.0Gbps PCIexpress Gen2 signals on one path, and DP 1.1 signals on the second path


    Original     		PDF PI3PCIE2612-A -35dB 56-Contact 56-contact, PD-2024 PI3PCIE2612-AZFE PS8925D display 40 pin connector pinout

    Application Note AN1108

    Abstract: AN918 AN-903 DS92LV090 DS92LV090A DS92LV090ATVEH AN1108 AN-808 lvds 40 pinout AN-918
    Text: ご注意：この日本語データシートは参考資料として提供しており内容が最新でない 場合があります。製品のご検討およびご採用に際しては、必ず最新の英文デー タシートをご確認ください。


    Original     		PDF DS92LV090A 100mV DS100111 nat2000 AN918; AN1108 DS92LV090A 64-Lead DS92LV090ATVEH Application Note AN1108 AN918 AN-903 DS92LV090 DS92LV090ATVEH AN1108 AN-808 lvds 40 pinout AN-918

    OD-S524-SC-MM

    Abstract: OD-J6863-0A01 OD-S524-MU-MM cletop HA01 OD-J6863-HA01 OD-S524-FCPC-MM
    Text: OE HYBRID 622.08Mbps Receiver OD-J6863-0A01/ HA01 OC-12: SR, IR-1, IR-2, LR-1, LR-2 and LR-3 STM-4: I-4, S-4.1, S-4.2, L-4.1, L-4.2 and L-4.3 1 Copyright C 1994-2001 NEC Corporation 11th September, 2001 Rev.8 - Contents 1. PRODUCT NUMBER . 3


    Original     		PDF 08Mbps OD-J6863-0A01/ OC-12: OD-S524-SC-MM OD-J6863-0A01 OD-S524-MU-MM cletop HA01 OD-J6863-HA01 OD-S524-FCPC-MM

    1310p

    Abstract: SY58609U SY58610U SY58611U
    Text: SY58610U 3.2Gbps Precision, LVPECL 2:1 MUX with Internal Termination and Fail Safe Input General Description The SY58610U is a 2.5/3.3V, high-speed, fully differential LVPECL 2:1 MUX capable of processing clock signals up to 2.5GHz and data patterns up to


    Original     		PDF SY58610U SY58610U 10pspp 100mV 200mVPP) M9999-082907-C 1310p SY58609U SY58611U

    1310p

    Abstract: 609U SY58609U SY58609UMG SY58609UMGTR SY58610U SY58611U
    Text: SY58609U 4.25Gbps Precision, CML 2:1 MUX with Internal Termination and Fail Safe Input General Description The SY58609U is a 2.5/3.3V, high-speed, fully differential CML 2:1 MUX capable of processing clock signals up to 2.5GHz and data patterns up to 4.25Gbps.


    Original     		PDF SY58609U 25Gbps SY58609U 25Gbps. 10pspp 100mV 200mVpp) M9999-082907-C 1310p 609U SY58609UMG SY58609UMGTR SY58610U SY58611U

    Untitled

    Abstract: No abstract text available
    Text: CY7C12411KV18, CY7C12561KV18 CY7C12431KV18, CY7C12451KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions ■


    Original     		PDF 36-Mbit CY7C12411KV18, CY7C12561KV18 CY7C12431KV18, CY7C12451KV18 CY7C12561KV18, CY7C12451KV18

    ICS853052

    Abstract: ICS853052AG ICS853052AGLF ICS853052AGT MC100EP58 MO-187 circuit diagram of 32-1 multiplexer marking 52AL
    Text: PRELIMINARY ICS853052 DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS853052 is a Dual LVCMOS / LVTTL-toICS Differential 2.5V, 3.3V, 5V LVPECL Multiplexer and HiPerClockS a member of the HiPerClocks™ family of High


    Original     		PDF ICS853052 ICS853052 199707558G ICS853052AG ICS853052AGLF ICS853052AGT MC100EP58 MO-187 circuit diagram of 32-1 multiplexer marking 52AL

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36)


    Original     		PDF CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit CY7C11571KV18, CY7C11501KV18 3M Touch Systems

    Untitled

    Abstract: No abstract text available
    Text: CY7C12411KV18, CY7C12561KV18 CY7C12431KV18, CY7C12451KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions ■


    Original     		PDF 36-Mbit CY7C12411KV18, CY7C12561KV18 CY7C12431KV18, CY7C12451KV18 CY7C12561KV18, CY7C12451KV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 450 MHz Clock for High Bandwidth


    Original     		PDF CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit CY7C11571KV18, CY7C11501KV18 CY7C11461KV18)

    Untitled

    Abstract: No abstract text available
    Text: SY58610U 3.2Gbps Precision, LVPECL 2:1 MUX with Internal Termination and Fail Safe Input General Description The SY58610U is a 2.5/3.3V, high-speed, fully differential LVPECL 2:1 MUX capable of processing clock signals up to 2.5GHz and data patterns up to


    Original     		PDF SY58610U SY58610U 10pspp 100mV 200mVPP) M9999-082907-C

    Untitled

    Abstract: No abstract text available
    Text: SY58609U 4.25Gbps Precision, CML 2:1 MUX with Internal Termination and Fail Safe Input General Description The SY58609U is a 2.5/3.3V, high-speed, fully differential CML 2:1 MUX capable of processing clock signals up to 2.5GHz and data patterns up to 4.25Gbps.


    Original     		PDF SY58609U 25Gbps SY58609U 25Gbps. 10pspp 100mV 200mVpp) M9999-082907-C

    m68000 microprocessor users manual

    Abstract: EC000 M68000 M68300 MC68000 MC68020 MC68EC000 bcd verilog 32-bit microprocessor architecture "Single-Port RAM"
    Text: Order This Document by M68300/D MOTOROLA SEMICONDUCTOR PRODUCT INFORMATION Custom 68300 Product Brief Custom 68300 Integrated Processors Motorola's Custom 68300 integrated processors allow the designers of high-volume digital systems to place their application-specific circuitry on chip with an M68000 family


    Original     		PDF M68300/D M68000 M68000 m68000 microprocessor users manual EC000 M68300 MC68000 MC68020 MC68EC000 bcd verilog 32-bit microprocessor architecture "Single-Port RAM"

    Untitled

    Abstract: No abstract text available
    Text: SY58610U 3.2Gbps Precision, LVPECL 2:1 MUX with Internal Termination and Fail Safe Input General Description The SY58610U is a 2.5/3.3V, high-speed, fully differential LVPECL 2:1 MUX capable of processing clock signals up to 2.5GHz and data patterns up to


    Original     		PDF SY58610U SY58610U 10pspp 100mV 200mVPP) M9999-082907-C

    Untitled

    Abstract: No abstract text available
    Text: SY58609U 4.25Gbps Precision, CML 2:1 MUX with Internal Termination and Fail Safe Input General Description The SY58609U is a 2.5/3.3V, high-speed, fully differential CML 2:1 MUX capable of processing clock signals up to 2.5GHz and data patterns up to 4.25Gbps.


    Original     		PDF SY58609U 25Gbps SY58609U 25Gbps. 10pspp 100mV 200mVpp) M9999-082907-C

    Untitled

    Abstract: No abstract text available
    Text: OBSOLETE DS92LV090AEP www.ti.com SNLS184B – JANUARY 2005 – REVISED APRIL 2013 DS92LV090AEP 9 Channel Bus LVDS Transceiver Check for Samples: DS92LV090AEP FEATURES DESCRIPTION • • • • • The DS92LV090AEP is one in a series of Bus LVDS transceivers designed specifically for the high speed,


    Original     		PDF DS92LV090AEP SNLS184B DS92LV090AEP 800ps 200mV

    85301AK

    Abstract: ICS85301 ICS85301AK ICS85301AKT MO-220
    Text: PRELIMINARY Integrated Circuit Systems, Inc. ICS85301 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS85301 is a high performance 2:1 Differential-to-LVPECL Multiplexer and a member of the HiPerClockS HiPerClockS™ family of High Performance Clock


    Original     		PDF ICS85301 ICS85301 85301AK 85301AK ICS85301AK ICS85301AKT MO-220

    Untitled

    Abstract: No abstract text available
    Text: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 450 MHz Clock for High Bandwidth


    Original     		PDF CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit CY7C11571KV18, CY7C11501KV18 CY7C11461KV18)