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    2N2007E

    Abstract: 2N2007 CAP 10nF 50V 0603 18126D107MAT 597D108X06
    Text: MIC5162 Dual Regulator Controller for DDR3 GDDR3/4/5 Memory and High-Speed Bus Termination General Description Features The MIC5162 is a dual regulator controller designed for highspeed bus termination. It offers a simple, low-cost JEDEC compliant solution for terminating high-speed, lowvoltage digital buses i.e. DDR, DD2, DDR3, SCSI, GTL,


    Original     		PDF MIC5162 MIC5162 M9999-061509 2N2007E 2N2007 CAP 10nF 50V 0603 18126D107MAT 597D108X06

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    Abstract: No abstract text available
    Text: MIC5163 Dual Regulator Controller for DDR3 GDDR3/4/5 Memory Termination General Description Features The MIC5163 is a dual regulator controller designed • 0.75V to 6V input supply voltage specifically for low voltage memory termination • Memory termination for: DDR3, GDDR3/4/5


    Original     		PDF MIC5163 MIC5163 M9999-042209-A

    2N2007

    Abstract: 2N2007E ddr3 termination 18126D107MAT ddr3 SSN SOT-23 SANYO 1000uF 35V MSOP-10 SUD50N02-06P tp1322
    Text: MIC5163 Dual Regulator Controller for DDR3 GDDR3/4/5 Memory Termination General Description Features The MIC5163 is a dual regulator controller designed • 0.75V to 6V input supply voltage specifically for low voltage memory termination • Memory termination for: DDR3, GDDR3/4/5


    Original     		PDF MIC5163 MIC5163 M9999-042209-A 2N2007 2N2007E ddr3 termination 18126D107MAT ddr3 SSN SOT-23 SANYO 1000uF 35V MSOP-10 SUD50N02-06P tp1322