256PIN Search Results

QFP256

Abstract: QFP256 Package QFP256-P-2828-0
Contextual Info: 256P6J-E Plastic 256pin 28✕28mm body QFP EIAJ Package Code QFP256-P-2828-0.40 Weight g 5.48 JEDEC Code – Lead Material Cu Alloy HD Under Planning D 256 193 192 E HE 1 Symbol 129 64 65 128 A L1 F b A1 c A2 e y L Detail F A A1 A2 b c D E e HD HE L L1 y

Contextual Info: 256F7X-A/B EIAJ Package Code – 256pin 27✕27mm body BGA JEDEC Code – E E1 D D1 Weight g – A e φb Y W V U T R P N M L K J H G F E D C B A Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 y A1 A A1 b D D1 E E1 e y Dimension in Millimeters Min

Contextual Info: 256F7B 256pin 27✕27mm body BGA EIAJ Package Code – JEDEC Code – Weight g y E D A A2 e φb Y W V U T R P N M L K J H G F E D C B A Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A3 A1 A A1 A2 A3 b D E e y Dimension in Millimeters Min Nom Max

HQFP256-P-2828-0

Abstract: CA2E
Contextual Info: 256P6K-E Plastic 256pin 28✕28mm body HQFP EIAJ Package Code HQFP256-P-2828-0.40 Weight g JEDEC Code – Under Planning HD D 256 Lead Material Cu Alloy 193 E HE 192 1 Symbol 64 129 128 65 A L1 F b y A1 c A2 e L Detail F A A1 A2 b c D E e HD HE L L1 y Dimension in Millimeters

CAD15-CAD8

Contextual Info: PCI1250A PC CARD CONTROLLER XCPS014 -D E C E M B E R 1997 * Peripheral Component Interconnect PCI Power Management Compliant • Supports Zoom Video With Internal Buffering • ACP11.0 Compliant • Programmable Output Select for CLKRUN • Packaged in 256-Pin BGA

PCI1251B

Contextual Info: PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 D D D D D D D D D D D D D D D D D PCI Power Management 1.0 Compliant ACPI 1.0 Compliant Packaged in GFN 256-Pin BGA or GJG MicroStar BGA PCI Local Bus Specification Revision 2.2 Compliant 1997 PC Card Standard Compliant

w12 diode

Abstract: PCI4450 PC MOTHERBOARD schematic diagram
Contextual Info: PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 D 1997 PC Standard Compliant D PCI Bus Power Management Interface D D D D D D D D D D D D D D D D D D D D Specification 1.1 Compliant ACPI 1.0 Compliant PCI Local Bus Specification Revision

CHIP EPROM AE12

Abstract: spru402 ST2328
Contextual Info: TMS320C6201 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS051G – JANUARY 1997 – REVISED NOVEMBER 2000 D High-Performance Fixed-Point Digital D D D D D D Signal Processor DSP TMS320C6201 – 5-ns Instruction Cycle Time – 200-MHz Clock Rate – Eight 32-Bit Instructions/Cycle

C6701

Contextual Info: TMS320C6701 FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR SPRS067E – MAY 1998 – REVISED MAY 2000 D Highest Performance Floating-Point Digital D D D D D Signal Processor DSP TMS320C6701 – 8.3-, 6.7-, 6-ns Instruction Cycle Time – 120-, 150-, 167-MHz Clock Rate

c6000 flash

Abstract: TMDX320006211
Contextual Info: TMS320C6211 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR TMS320C6711 FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR SPRS073C – AUGUST 1998 – REVISED JUNE 2000 D D D Processors DSPs Fixed-Point: TMS320C6211 Floating-Point: TMS320C6711 – 10-, 6.7-ns Instruction Cycle Time

TEXAS INSTRUMENTS, Mold Compound, CSP

Contextual Info: SM320C6202ĆEP FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SGUS044–JULY 2003 D Controlled Baseline D D D D D D D D D D 3M-Bit On-Chip SRAM – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 105°C Enhanced Diminishing Manufacturing

Contextual Info: SM320C6711ĆEP, SM320C6711BĆEP, SM320C6711CĆEP, SM320C6711DĆEP FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS SGUS054A − AUGUST 2004 − REVISED SEPTEMBER 2005 D Controlled Baseline D D D D D D D D L1/L2 Memory Architecture − One Assembly/Test Site, One Fabrication

Contextual Info: BCM8705 SERIAL 10-GIGABIT ETHERNET/FIBRE CHANNEL TRANSCEIVER WITH WIS LAYER AND XAUI INTERFACE SUMMARY OF BENEFITS FEATURES • Fully integrated CMU, CDR, SerDes, Limiting Amplifier, • Best performance for LAN 10GbE and WAN (OC-192 • Supports Broadcom’s StrataXGS® Ethernet Switches Service

Contextual Info: BCM5387 5-GE PORT SWITCH WITH INTEGRATED SERDES FEATURES SUMMARY OF BENEFITS • Highest silicon integration level achieved for a 5-port, 10/100/ • Enables a new generation of lower-cost switches with Gigabit 1000 Ethernet switch device • Eighth-generation switch on a chip

ep4cgx30f484

Abstract: EP4CE115 CYIV-5V1-1 EP4CGX EP4CE55 EP4CE15 sigma delta lcd screen lvds 40 pin diagram ep4ce22 ep4ce40
Contextual Info: Cyclone IV Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com CYIV-5V1-1.5 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

C6000

Abstract: TMS320C6000 TMS320C6411
Contextual Info: TMS320C6411 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS196I − MARCH 2002 − REVISED JUNE 2005 D Low-Cost, High-Performance Fixed-Point D D D D DSP − TMS320C6411 − 3.33-ns Instruction Cycle Time − 300-MHz Clock Rate − Eight 32-Bit Instructions/Cycle

Using the TMS320C674x BootLoader

Contextual Info: TMS320C6743 SPRS565B – APRIL 2009 – REVISED JUNE 2011 www.ti.com TMS320C6743 Fixed/Floating-Point Digital Signal Processor Check for Samples: TMS320C6743 1 TMS320C6743 Fixed/Floating-Point Digital Signal Processor 1.1 Features 12 • Highlights – Up to 375-MHz FIxed/Floating-Point VLIW

5M80ZT100

Abstract: 5M570ZM100 5M2210ZF256 5M160ZE64 5m240Zt100 5M1270ZF324 5m570ZT144 EP4CE15F17 5M40ZE64A5 5M1270ZT
Contextual Info: The Automotive-Grade Device Handbook The Automotive-Grade Device Handbook 101 Innovation Drive San Jose, CA 95134 www.altera.com AUT5V1-2.0 Document last updated for Altera Complete Design Suite version: Document publication date: 11.0 May 2011 Subscribe 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.

AIN101

Abstract: AIN113 AIN-34 AIN50 LA1245 1840a sp2a2 circuit diagram of 32-1 multiplexer AIN25 AIN61
Contextual Info: SPACE ELECTRONICS INC. 128 CHANNEL MULTIPLEXER SPACE PRODUCTS 81840RP ADDRESS ENABLE COMMON TO ALL INPUT MUX's 8 16 ADDRESS ENABLE CLAMP/ PRECHARGE 4 8 16:1 1840A IN CASCADE INPUT BYPASS ADDRESS ENABLE 7 5 5 GRND IN IN 16 V -15V 4 GRND 128 TOTAL ANALOG INPUTS

antifuse programming technology

Abstract: 40MX 42MX A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 42MX24
Contextual Info: v6.0 40MX and 42MX FPGA Families Fe a t ur es High C apaci t y • • • • • • Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages Single-Chip ASIC Alternative 3,000 to 54,000 System Gates Up to 2.5 kbits Configurable Dual-Port SRAM

00XXX001

Abstract: BA 5979 R15C3 OR3T125 OR3T20 OR3T30 OR3T55 PT10 PT11 PT12
Contextual Info: Data Sheet November 2006 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Baseline FPGA family used in Series 3+ FPSCs field programmable system chips which combine FPGA logic

A1280A VKS

Abstract: A1280A-CQ172C VKS FPGA CQFP 106 actel a1280a unused pin VKS FPGA CQFP 172 antifuse programming technology A14100A-CQ256C fpga radiation A1280A ACTEL A1280A
Contextual Info: PRELIMINARY SPACE ELECTRONICS INC. SPACE PRODUCTS RADIATION TOLERANT RAD-PAK FIELD PROGRAMMABLE GATE ARRAYS FEATURES GENERAL DESCRIPTION Radiation Characteristics Actel builds the most reliable field programmable gate arrays FPGAs in the industry, with overall antifuse reliability ratings of less than 10 failures-in-time (FITs), corresponding to a useful life of more than 40 years.

ad 161

Abstract: vhdl code PN code generator ad 152 transistor ad 153 transistor S-108 PF144 PQ208 QL5130 QL5130-33APF144C QL5130-33APQ208C
Contextual Info: QL5130 - QuickPCITM 33 MHz/32-bit PCI Target with Embedded Programmable Logic and Dual Port SRAM last updated 12/1099 Device Highlights DEVICE HIGHLIGHTS Q8DÃ7ˆ†Ã±Ã""ÃHC“Ã"!Ãiv‡†Ãqh‡hÃhqÃhqq…r†† High Performance PCI Controller • 32-bit / 33 MHz PCI Target

ultrasparc

Contextual Info: UltraSPARC “-!! Data Buffer UDB-II DATA SHEET Companion Device for 250/300 MHz UltraSPARC-II Systems D e s c r ip t io n The UltraSPARC-II Data Buffer (UDB-II) consists of two identical ASICs connecting the UltraSPARC-II micro­ processor and its E-Cache to the system data bus (i.e., UPA bus). These two are designated UDB_H (for the