R0506

Contextual Info: CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 IDT72103 IDT72104 Integrated Device Technology, Inc. FEATURES: APPLICATIONS: • 35ns parallel port access time, 45ns cycle time • 50MHz serial input/output frequency • Serial-to-parallel, parallel-to-serial, serial-to-serial, and

Contextual Info: 3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO IDT72V81 DUAL 512 X 9, DUAL 1024 x 9 IDT72V82 PRELIMINARY INFORMATION Integrated Device Technology, Inc. FEATURES: single package with all associated control, data, and flag lines assigned to separate pins. The devices use Full and Empty

49C466

Contextual Info: 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT IDT49C466 IDT49C466A FEATURES: DESCRIPTION: • 64-bit wide Flow-thruEDC • Separate System and Memory Data Input/Output Buses • — Error Detect Time: 10ns — Error Correct Time: 15ns • Corrects all single bit errors; Detects all double bit errors

Contextual Info: March 1994 iiv f ili DATA SHEET_ _ M 67203/ M 67204 2K x 9 & 4K x 9 CMOS PARALLEL FIFO FEATURES . . . . . FIRST-IN FIRST-OUT DUAL PORT MEMORY 2048 x 9 ORGANISATION M 67203 4096 x 9 ORGANISATION (M 67204) FAST ACCESS TIME COMMERCIAL : 20*, 25,35,45, 55 ns

Contextual Info: MAR i2 1393 CS4231 DRAFT Semiconductor Corporation Parallel Interface Multimedia Audio Codec Features General Description • ADPCM Compression/Decompression • Integrated parallel Interface to ISA and EISA buses • Support for stereo digital audio at sample rates from 4 kHz to 50 kHz

Contextual Info: BURR - BROWN I DAC7615 1 Serial Input, 12-Bit, Quad, Voltage Output DIGITAL-TO-ANALOG CONVERTER FEATURES APPLICATIONS • LOW POWER: 20mW • PROCESS CONTROL • UNIPOLAR OR BIPOLAR OPERATION • ATE PIN ELECTRONICS • SETTLING TIME: 10 is to 0.012% • CLOSED-LOOP SERVO-CONTROL

CS4231

Abstract: CS4231-KL AD1848 CS4231-KQ CS4248 CAPACITOR MICROPHONE mce XTAL-11 rigol microchannel
Contextual Info: MAR 12 1393 CS4231 DRAFT Semiconductor Corporation Parallel Interface Multimedia Audio Codec Features General Description • ADPCM Compression/Decompression • Integrated parallel Interface to ISA and EISA buses • Support for stereo digital audio at sample rates from 4 kHz to 50 kHz

IDT7201SA

Abstract: XRNP IDT7200S 7201SA
Contextual Info: CMOS PARALLEL FIRST-IN/FIRST-OUT FIFO 256 X 9-BIT & 512 X 9-BIT IDT7200S/L IDT7201SA/LA Integrated Device Technology, inc. FEATURES: DESCRIPTION: • • • • The IDT7200/7201A are dual-port mem ories that load and empty data on a first-in/first-out basis. The devices use Full

f 7205

Abstract: L 7206 ta 7205
Contextual Info: |efty In te g rate d DevIc e Technology, Inc. CMOS PARALLEL FIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT, 4096 x 9-BIT, 8192 x 9-BIT & 16384 x 9-BIT IDT7203 IDT7204 IDT7205 IDT7206 FEATURES: DESCRIPTION: • • • • • • • The IDT7203/7204/7205/7206 are dual-port memories buff­

D2B1

Abstract: u706
Contextual Info: Î CMOS ASYNCHRONOUS FIFO 2 5 6 x 9 , 5 1 2 x 9 , 1KX 9 dt) IDT7200L IDT7201LA IDT7202LA In te g rate d D<ïv ic e Technology, Inc. FEATURES: • • • • • • • • • • • • • • Full and Empty flags to prevent data overflow and underflow

Contextual Info: IDT72103 IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 X 9, 4096 x 9 Integrated Device Technology, Inc. APPLICATIONS: FEATURES: • • • • • • • • • • • High-speed data acquisition systems Local area network LAN buffer High-speed modem data buffer

Contextual Info: LH5492 4 K x 9 Clocked FIFO FEATURES status output signals are synchronized to these clocks, to simplify system design. The input and output ports oper­ ate altogether independently of each other, except when the FIFO becomes either totally full or else totally empty.

aei cr

Abstract: a04l
Contextual Info: ADVANCE INFORMATION LH54V3611/21 FEATURES • Upwards-Compatible with Sharp LH543611/21 • Cycle Time as fast as 15 ns • Two 512 x 36-bit FIFO Buffers LH54V3611 or Two 1024 x 36-bit FIFO Buffers (LH54V3621) • Selectable 36/18/9-bit Word Width on Port B;

relay lzl

Abstract: k3n omron Scans-031 SSC 9500
Contextual Info: Period Meter omRon K3NP Period Meter Operation Manual Produced January 1998 iv Notice: OMRON products are manufactured for use according to proper procedures by a qualified operator and only for the purposes described in this manual. The following conventions are used to indicate and classify precautions in this manual. Always heed

Contextual Info: CMOS ASYNCHRONOUS FIFO 256x9, 5 1 2 x 9 ,1Kx 9 IDT7200L IDT7201 LA IDT7202LA Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • • • • First-In/First-O ut dual-port memory 256 x 9 organization IDT7200 512 x 9 organization (IDT7201)

CY7C4281

Abstract: CY7C4291 IDT72201
Contextual Info: fax id: 5415 ; M : : W CYPRESS CY7C4281 CY7C4291 PRELIMINARY 64K/128Kx9 Deep Sync FIFOs • Pin-compatible density upgrade to IDT72201 /1 1/21 /31/41 /51 Features • High-speed, low-power, first-in first-out FIFO memories • 64k x 9 (CY7C4281) • 128k x 9 (CY7C4291)

Contextual Info: Advanced Micro Devices Am4601 Programmable-Flags, 512 x 9 FIFO DISTINCTIVE CHARACTERISTICS • 512 x 9 RAM-based FIFO ■ 25 and 35 ns access times ■ Two fixed flags; full and empty ■ Two programmable flags; programmable from 1 to 511 ■ ■ Programmable polarity for all four flags

top 256 yn

Contextual Info: CMOS ASYNCHRONOUS FIFO 256x9, 5 1 2 x 9 , 1Kx 9 IDT7200L IDT7201LA IDT7202LA Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • • • • First-In/First-O ut dual-port m em ory 256 x 9 organization IDT7200 512 x 9 organization (ID T7201)

Contextual Info: QS72231, QS72241 ADVANCE INFORMATION Q High-Speed CMOS 2K x 9, 4K x 9 Parallel Clocked FIFO QS72231 QS72241 FEATURES • • • • 15-ns 66-MHz read/write cycle times Synchronous/asynchronous read and write TTL input and output level compatible Low power with industry-standard pinouts

IDT72103

Abstract: IDT72104 STATUS11
Contextual Info: IDT72103 IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT Integ rated D evice Technology, Inc* FEATURES: APPLICATIONS: • • • • • • • • • • • • 35ns pa rallel po rt access tim e, 4 5 ns c ycle tim e 50M H z serial inpu t/o u tp u t fre que ncy

la30 7201

Abstract: dt7201
Contextual Info: CMOS ASYNCHRONOUS FIFO 256x9, 5 1 2 x 9 , 1Kx 9 IDT7200L IDT7201LA IDT7202LA Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • • • • Full and Empty flags to prevent data overflow and underflow and expansion logic to a llo w fo r unlimited expansion capability

Mbbfl03

Abstract: DDD1141
Contextual Info: QS72231, QS72241 ADVANCE INFORMATION Q High-Speed CMOS 2K X 9, 4K X 9 Parallel Clocked FIFO QS72231 QS72241 FEATURES • • • • 15-ns 66-MHz read/write cycle times Synchronous/asynchronous read and write TTL input and output level compatible Low power with industry-standard pinouts

B1340

Abstract: SSOP16 UAA2078M 8 channel RF Control Circuit UAA2079 2079M philips dect UAA2079M
Contextual Info: Objective specification Philips Semiconductors Zero IF front-end receiver for DECT applications_ UAA2078M FEATURES GENERAL DESCRIPTION • B alanced R F input T h e U A A 207 8M is a low -pow er front-end for use with the U A A 207 9M baseband part in a zero IF D E C T receiver. It

Contextual Info: / 4096X9-BitRFO-Radiation Hardened 7204ERP Epi - CMOS Parallel Cascadeable FIFO QS2 In » DATA INPUTS Do - D b For Space Applications W- WRITE CONTROL m nT'n EH RAM ARRAY Z 12048 x 9 \ r 4096 X 9 8192x9 16384 x 9 WRITE POINTER THREESTATE BUFFERS S e I' s 7204ERP (RP for