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TDK Corporation B66461KX187 Ferrite Core ELP Core 43.2mm 27.9mm 9.5mm General Application - Trays (Alt: B66461K0000X187)
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Avnet Americas	B66461KX187	Tray		12 Weeks	900	1 - 10 - 100 - 1000 $3.78967 10000 $3.78967	Buy Now
Avnet Abacus	B66461KX187			10 Weeks	900	1 - 10 - 100 - 1000 - 10000 -	Buy Now
TDK Corporation B66291KX187 Ferrite Core Inductor with Clamp Recess 8500nH N87 100kHz - Trays (Alt: B66291K0000X187)
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Avnet Americas	B66291KX187	Tray		12 Weeks	450	1 - 10 - 100 - 1000 $3.86167 10000 $3.86167	Buy Now
Avnet Abacus	B66291KX187			16 Weeks	150	1 - 10 - 100 - 1000 - 10000 -	Buy Now
TDK Corporation B66281KX187 Ferrite Core I Core 14mm 5mm 3.5mm General Application - Bag (Alt: B66281K0000X187)
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Avnet Americas	B66281KX187	Bag		27 Weeks	4,800	1 - 10 - 100 - 1000 - 10000 $0.86812	Buy Now
Avnet Abacus	B66281KX187			25 Weeks	4,800	1 - 10 - 100 - 1000 - 10000 -	Buy Now
TDK Corporation B66281K0000X187 Ferrite Cores & Accessories I14/1.5/5 N87 1250 +25% -25%
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Mouser Electronics	B66281K0000X187		3,338			1 $1.07 10 $0.902 100 $0.599 1000 $0.599 10000 $0.598	Buy Now
TDK Corporation B66461K0000X187 Ferrite Cores & Accessories I43/4/28 N87 8500 +25% -25%
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Mouser Electronics	B66461K0000X187		1,882			1 $5.42 10 $3.69 100 $2.62 1000 $2.61 10000 $2.61	Buy Now

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1KX18 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
C4558 Abstract: C4554 C4557 c455 CY7C455-14JI CY7C455 CY7C456 CY7C457 CY7C447 Text: CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags • Depth Expansion Capability • 52-pin PLCC and 52-pin PQFP Features • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455)	Original	CY7C455 CY7C456 CY7C457 52-pin CY7C455) CY7C456) CY7C457) 83-MHz C4558 C4554 C4557 c455 CY7C455-14JI CY7C455 CY7C456 CY7C457 CY7C447	PDF
723653 Abstract: 72V7290 72V3613 72V7250 72V3611 72V3623 72V72100 72V7230 72V7240 72V7260 Text: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. July’00 IDT FIFO Memory Products Quick Reference Guide	Original	512-bit 16K-bit 64K-bit 128K-bit 256K-bit 512K-bit 100MHz 133MHz 723653 72V7290 72V3613 72V7250 72V3611 72V3623 72V72100 72V7230 72V7240 72V7260	PDF
xc3s500e fg320 Abstract: intel strataflash j3d SPARTAN 3E STARTER BOARD transistor tt 2222 pin configuration 500K variable resistor eeprom programmer schematic winbond AT45DB AT49 jtag cable Schematic XC3S500E spartan 3a Text: Spartan-3E FPGA Family: Complete Data Sheet R DS312 April 18, 2008 Product Specification Module 1: Introduction and Ordering Information Module 3: DC and Switching Characteristics DS312-1 v3.7 April 18, 2008 DS312-3 (v3.7) April 18, 2008 • • • •	Original	DS312 DS312-1 DS312-3 DS312-2 XC3S500E VQG100 DS312-4 xc3s500e fg320 intel strataflash j3d SPARTAN 3E STARTER BOARD transistor tt 2222 pin configuration 500K variable resistor eeprom programmer schematic winbond AT45DB AT49 jtag cable Schematic spartan 3a	PDF
723653 Abstract: BI 7284 72V7250 72V72100 72V7230 72V7240 72V7260 72V7270 72V7280 72V7290 Text: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. Jan’00 IDT FIFO Memory Products Quick Reference Guide	Original	512-bit 16K-bit 64K-bit 128K-bit 512K-bit 7236x3/72V36x3 723653 BI 7284 72V7250 72V72100 72V7230 72V7240 72V7260 72V7270 72V7280 72V7290	PDF
xc3s500e vq100 Abstract: No abstract text available Text: 1 Spartan-3E FPGA Family Data Sheet DS312 July 19, 2013 Product Specification Module 1: Introduction and Ordering Information Module 3: DC and Switching Characteristics DS312 v4.1 July 19, 2013 DS312 (v4.1) July 19, 2013 • Introduction • • Features	Original	DS312 DS312 xc3s500e vq100	PDF
verilog code for dual port ram with axi interface Abstract: XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0 Text: LogiCORE IP Block Memory Generator v7.1 DS512 April 24, 2012 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Block Memory Generator BMG core is an advanced memory constructor that generates area and performance-optimized memories	Original	DS512 verilog code for dual port ram with axi interface XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0	PDF
C4558 Abstract: c455 CY7C455 CY7C456 CY7C457 CY7C447 Text: 57 CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags Features • Depth Expansion Capability • 52-pin PLCC and 52-pin PQFP • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455)	Original	CY7C455 CY7C456 CY7C457 52-pin CY7C455) CY7C456) CY7C457) 83-MHz C4558 c455 CY7C455 CY7C456 CY7C457 CY7C447	PDF
MULT18X18 Abstract: block diagram of 8 bit array multiplier block diagram of 16 bit array multiplier Text: Applications CORE Generator Designing High-Performance Memories and Multipliers It is easy to create efficient, high-performance designs using the Xilinx CORE Generator . by Krista M. Marks Engineering Manager, IP Solutions Division, Xilinx Inc. krista.marks@xilinx.com	Original	18x18 MULT18X18 36-bit block diagram of 8 bit array multiplier block diagram of 16 bit array multiplier	PDF
schematic diagram atx Power supply 500w Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS Text: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 Digital Signal Processors, iCoupler , iMEMS® and iSensor . . . . . 805, 2707, 2768-2769 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-568 RF Connectors . . . . . . . . . . . . . . . . . . . . . . Pages 454-455	Original	P462-ND P463-ND LNG295LFCP2U LNG395MFTP5U US2011) schematic diagram atx Power supply 500w pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS	PDF
C4558 Abstract: C4557 c4552 C4555 c4556 C-4555 c4554 c455 CY7C455 CY7C457 Text: 57 CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags Features • Depth Expansion Capability • 52-pin PLCC and 52-pin PQFP • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455)	Original	CY7C455 CY7C456 CY7C457 52-pin CY7C455) CY7C456) CY7C457) 83-MHz C4558 C4557 c4552 C4555 c4556 C-4555 c4554 c455 CY7C455 CY7C457	PDF
xc3s1200e fg320 Abstract: XC3S250E vqg100 SST25LFxxxA xc3s100 LVCMOS12 XC3S500E-FT256 Macronix Lot Identifier XC3S1200E-FG320 IPL34 MX25Lxxxx Text: Spartan-3E FPGA Family: Complete Data Sheet R DS312 November 23, 2005 Advance Product Specification Module 1: Introduction and Ordering Information Module 3: DC and Switching Characteristics DS312-1 v2.0 November 23, 2005 8 pages DS312-3 (v2.0) November 23, 2005	Original	DS312 DS312-1 DS312-3 DS312-2 FG400 DS312-1, DS312-2, DS312-3, DS312-4, DS312-4 xc3s1200e fg320 XC3S250E vqg100 SST25LFxxxA xc3s100 LVCMOS12 XC3S500E-FT256 Macronix Lot Identifier XC3S1200E-FG320 IPL34 MX25Lxxxx	PDF
XC3S100E TQG144 Abstract: XC3S500E FGG320 FR 309 diode Text: Spartan-3E FPGA Family: Complete Data Sheet R DS312 May 19, 2006 Preliminary Product Specification Module 1: Introduction and Ordering Information Module 3: DC and Switching Characteristics DS312-1 v3.0 March 22, 2006 DS312-3 (v3.2) May 19, 2006 • •	Original	DS312 DS312-1 DS312-3 DS312-2 XC3S100E CP132 XC3S1600E FG320 XC3S100E TQG144 XC3S500E FGG320 FR 309 diode	PDF
FSQ510 Equivalent Abstract: BTA12 6008 bta16 6008 ZIGBEE interface with AVR ATmega16 Precision triac control thermostat thyristor t 558 f eupec gw 5819 diode transistor a564 A564 transistor BSM25GP120 b2 Text: SEMICONDUCTORS MCU/MPU/DSP Atmel. . . . . . . . . 167, 168, 169, 170, 171, 172 Blackhawk. . . . . . . . . . . . . . . . . . . . . . . . . 173 Cyan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Cypress. . . . . . . . . . . . . . . 175, 176, 177, 178	Original	GP-20) FSQ510 Equivalent BTA12 6008 bta16 6008 ZIGBEE interface with AVR ATmega16 Precision triac control thermostat thyristor t 558 f eupec gw 5819 diode transistor a564 A564 transistor BSM25GP120 b2	PDF
723653 Abstract: 72V841 72825 72V3622 BI 7284 72V3613 723674 72V211 72V221 72V241 Text: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. July’99/PC IDT FIFO Memory Products Width	Original	99/PC 28-TP 36-bit 18-bit 723653 72V841 72825 72V3622 BI 7284 72V3613 723674 72V211 72V221 72V241	PDF

ug230 Abstract: xc3s500e fg320 intel strataflash j3d xc3s1200e fg320 M25PXX XAPP485 XC3S500E XC3S250E-PQ208 XC3S500E FGG320 matrix tv m21 service mode manual Text: Spartan-3E FPGA Family: Complete Data Sheet R DS312 May 29, 2007 Product Specification Module 1: Introduction and Ordering Information Module 3: DC and Switching Characteristics DS312-1 v3.4 November 9, 2006 DS312-3 (v3.6) May 29, 2007 • • • • •	Original	DS312 DS312-1 DS312-3 DS312-2 XC3S100E CP132 XC3S500E XC3S1600E DS312-4 ug230 xc3s500e fg320 intel strataflash j3d xc3s1200e fg320 M25PXX XAPP485 XC3S250E-PQ208 XC3S500E FGG320 matrix tv m21 service mode manual	PDF
256x16* STATIC RAM Abstract: AZ 280 memory 4Kx4 rom DS234 Text: Single-Port Block Memory v5.0 DS234 v0.1 November 1, 2002 Product Specification Features • Fully synchronous drop-in module for Virtex , Virtex-II, Virtex-II Pro™, Spartan™-II, Spartan-IIE, and Spartan-3 FPGAs • Supports all three Virtex-II write mode options:	Original	DS234 xcv800 xcv1000 xcv50E xcv100E xcv200E xcv300R xcv400E xcv600E xcv1000E 256x16* STATIC RAM AZ 280 memory 4Kx4 rom DS234	PDF
CY62256LL-PC Abstract: VIC068A-GC VIC64-NC VIC64-UMB PALCE22V10-JI PALC16L8Q PLD VME A113 CY7B923 JESD22-A113 Text: Cypress Semiconductor Product Reliability 1997 Published June, 1997 CYPRESS SEMICONDUCTOR PRODUCT RELIABILITY TABLE OF CONTENTS 1.0 OVERVIEW OF CYPRESS SEMICONDUCTOR TOTAL QUALITY MANAGEMENT SYSTEM. 1 2.0 ELECTRICAL AVERAGE OUTGOING QUALITY. 2	Original	PALCE22V10-JC FLASH-FL22D CY62256LL-PC VIC068A-GC VIC64-NC VIC64-UMB PALCE22V10-JI PALC16L8Q PLD VME A113 CY7B923 JESD22-A113	PDF
C4558 Abstract: C4557 c4554 c455 CY7C455 CY7C456 CY7C457 c4556 C4559 CY7C447 Text: fax id: 5408 1CY 7C45 7 CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags Features Functional Description • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455) • 1,024 x 18 (CY7C456)	Original	CY7C455 CY7C456 CY7C457 CY7C455) CY7C456) CY7C457) 83-MHz C4558 C4557 c4554 c455 CY7C455 CY7C456 CY7C457 c4556 C4559 CY7C447	PDF
manual SPARTAN-3 XC3S400 evaluation kit Abstract: hcl l21 usb power supply circuit diagram verilog code for Modified Booth algorithm vhdl code for lcd of spartan3E UG331 TT 2222 Horizontal Output Transistor pins out dia verilog for 8 point fft using FPGA spartan3 vhdl code for ldpc decoder types of multipliers ge fanuc cpu 331 Text: Spartan-3 Generation FPGA User Guide Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families UG331 v1.7 August 19, 2010 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development	Original	UG331 guides/ug332 manual SPARTAN-3 XC3S400 evaluation kit hcl l21 usb power supply circuit diagram verilog code for Modified Booth algorithm vhdl code for lcd of spartan3E UG331 TT 2222 Horizontal Output Transistor pins out dia verilog for 8 point fft using FPGA spartan3 vhdl code for ldpc decoder types of multipliers ge fanuc cpu 331	PDF
XC6SL Abstract: SPARTAN 6 Configuration SPARTAN-6 DS512 RAMB36 RAMB18 RAMB18SDP hamming decoder vhdl code spartan 3 multiprocessor 2Kx18 Text: Block Memory Generator v3.3 DS512 September 16, 2009 Product Specification Introduction • The Xilinx LogiCORE IP Block Memory Generator core is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs.	Original	DS512 XC6SL SPARTAN 6 Configuration SPARTAN-6 RAMB36 RAMB18 RAMB18SDP hamming decoder vhdl code spartan 3 multiprocessor 2Kx18	PDF
256x16* STATIC RAM Abstract: 32Kx1 false RAMB16 XC2S100 XC2S15 XC2S150 XC2S200 XC2S30 XC2S50 Text: Single-Port Block Memory Core v6.2 DS234 April 28, 2005 Features • Fully synchronous drop-in module for Virtex , Virtex-II, Virtex-II Pro, Virtex-4, Spartan™-II, Spartan-IIE, Spartan-3, and Spartan-3E FPGAs • Supports all three Virtex-II write mode options:	Original	DS234 256x16* STATIC RAM 32Kx1 false RAMB16 XC2S100 XC2S15 XC2S150 XC2S200 XC2S30 XC2S50	PDF
C4558 Abstract: c455 CY7C447 C4557 C4556 CY7C455 CY7C456 CY7C457 CY7C455-20JC Text: 57 CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags Features • Depth Expansion Capability • 52-pin PLCC and 52-pin PQFP • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455)	Original	CY7C455 CY7C456 CY7C457 52-pin CY7C455) CY7C456) CY7C457) 83-MHz C4558 c455 CY7C447 C4557 C4556 CY7C455 CY7C456 CY7C457 CY7C455-20JC	PDF
Untitled Abstract: No abstract text available Text: I 1K x 18-BIT - 2K x 9-BIT C M O S BiFlFO advance I NFORMATI ON IDT7252 In te g ra te d D e v ic e Tec h n 0 I 0 3 y Inc quadruple system throughput performance of the peripheral inter face by eliminating inefficiencies associated with widely varying, mismatched bus widths. The BiFlFO can handle data transfers be	OCR Scan	18-BIT IDT7252 16-bit 32-bit a1Kx18-bit 1Kx18-bit MIL-STD-883, IDT7252	PDF
vhdl code for fifo Abstract: free vhdl code sample vhdl code for memory write Text: VHDL Behavioral FIFO Models VHDL BEHAVIORAL FIFO MODELS DEVICES SUPPORTED MODEL INCLUDES PART NUMBER ORGANIZATION • Source Code LH5420 256 x 36 x 2 • Test Bench LH543620 1K x 36 • User's Documentation LH540215 5 12 x 18 • Free Technical Support LH540225	OCR Scan	1076-Compatible LH5420 LH543620 LH540215 LH540225 1Kx18 1-800-RAVICAD vhdl code for fifo free vhdl code sample vhdl code for memory write	PDF

1KX18 Search Results

1KX18 Price and Stock

TDK Corporation B66461KX187

TDK Corporation B66291KX187

TDK Corporation B66281KX187

TDK Corporation B66281K0000X187

TDK Corporation B66461K0000X187

1KX18 Datasheets Context Search

C4558

723653

xc3s500e fg320

723653

xc3s500e vq100

verilog code for dual port ram with axi interface

C4558

MULT18X18

schematic diagram atx Power supply 500w

C4558

xc3s1200e fg320

XC3S100E TQG144

FSQ510 Equivalent

723653

ug230

256x16* STATIC RAM

CY62256LL-PC

C4558

manual SPARTAN-3 XC3S400 evaluation kit

XC6SL

256x16* STATIC RAM

C4558

Untitled

vhdl code for fifo