PCD8571P
Abstract: signetics linear 1985 PCD3340 PCF84C00 7Z87 PCD8571 PCD8571D
Text: Signetics Linear Products Product Specification 1K Serial RAM PCD8571 GENERA L DESCRIPTION The PCD8571 is a low power 1024-bit static CMOS RAM organized as 128 words by 8-bits. Addresses and data are transferred serially via a two-line bidirectional bus l2C . The built-in word address register
|
OCR Scan
|
PCD8571
PCD8571
1024-bit
PCD8571P
signetics linear 1985
PCD3340
PCF84C00
7Z87
PCD8571D
|
PDF
|
PCD8571P
Abstract: PCD8571 PCD8571D signetics handbook MAB8400 PCD8571T PCF84C00 PCD3340 signetics linear sot151a
Text: P roduct Specification Signetics Linear Products 1K Serial RAM PCD8571 G E N E R A L DESCRIPTION The PCD8571 is a low power 1024-bit static CMOS RAM organized as 128 words by 8 -bits. Addresses and data are transferred serially via a tw o-line bidirectional bus t 2C . The b u ilt-in word address register
|
OCR Scan
|
PCD8571
PCD8571
1024-bit
PCD8571P
PCD8571D
signetics handbook
MAB8400
PCD8571T
PCF84C00
PCD3340
signetics linear
sot151a
|
PDF
|
ecall
Abstract: No abstract text available
Text: S-22 Series PARALLEL NON-VOLATILE RAM The S-22 Series is a non-volatile CMOS RAM, composed of a CMOS static RAM and a n on -vo latile e le c tric a lly era sab le and programmable memory E2PROM to backup the SRAM. The organization is 256-word x 4-bit (total 1K bits) for the S-22H12 and
|
OCR Scan
|
256-word
S-22H12
S-22S12,
64-word
S-22H10
S-22S10.
S-22H12:
X2212
S-22S12:
S-22H10:
ecall
|
PDF
|
msc 1330
Abstract: CF RX reset x7 APU4003 hrf1 transistor BCF 70
Text: APU4003 4-Bit Micro-Controller With LCD Driver, 1K Word Features y Control outputs: ALARM, LIGHT y LCD driver outputs can drive up to 75 LCD segments y Mask option to select 4 LCD drive modes: static, duplex (1/2 duty 1/2 bias, 1/3 duty 1/2 bias or 1/3
|
Original
|
APU4003
msc 1330
CF RX
reset x7
APU4003
hrf1
transistor BCF 70
|
PDF
|
APU4003
Abstract: transistor BCF 70 64x4-Bit TMS 1170
Text: APU4003 4-Bit Micro-Controller With LCD Driver, 1K Word Features y Control outputs: ALARM, LIGHT y LCD driver outputs can drive up to 75 LCD segments y Mask option to select 4 LCD drive modes: static, duplex (1/2 duty 1/2 bias, 1/3 duty 1/2 bias or 1/3
|
Original
|
|
PDF
|
APU4003T
Abstract: SEG22 SEG23 RY 101
Text: APU4003T 4-Bit Micro-Controller With EPROM, 1K Word Features y Control outputs: ALARM, LIGHT. y LCD driver outputs can drive up to 75 LCD segments . y PROM option to select 4 LCD drive modes: static, duplex (1/2 duty 1/2 bias, 1/3 duty 1/2 bias or 1/3 duty 1/3 bias).
|
Original
|
APU4003T
APU4003T
SEG22
SEG23
RY 101
|
PDF
|
Untitled
Abstract: No abstract text available
Text: SECTION 3 MEMORY CONFIGURATION MOTOROLA DSP56302UM/AD 3-1 Memory Configuration 3.1 3.2 3.3 3.4 3.5 3-2 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 RAM CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
|
Original
|
DSP56302UM/AD
DSP56302
24-bit
AA0564
16-bit
|
PDF
|
Untitled
Abstract: No abstract text available
Text: APLESSEY W PRELIMINARY INFORMATION S em ico n d u cto rs • MV61902 1K X 9 DIPSTICK" FIFO The MV61902 is one of a new generation of RAM-based FIFOs designed for ease of use. The MV61902 has a userprogrammable flag DIPSTICK which defaults to a conventional ‘half-full’ flag on power-up.
|
OCR Scan
|
MV61902
MV61902
10MHz
MV61902s
20MHz
2200mW
|
PDF
|
KM424C256Z
Abstract: SIMM 30-pin 30-pin SIMM RAM KM41C256P KM44C256bp KM41C1000BJ 257J KM44C256BZ 1K x4 static ram 30-pin simm memory "16m x 8"
Text: FUNCTION GUIDE MEMORY ICs 2. PRODUCT GUIDE 2.1 Dynamic RAM Part Number Capacity Organization Speed ns Technology Features Packages Remark 64K bit KM4164BP 100/120/150 NMOS Page Mode 16 Pin DIP Now 256K bit KM41C256P KM41C256J KM41C256Z KM41C257P KM41C257J
|
OCR Scan
|
KM4164BP
KM41C256P
KM41C256J
KM41C256Z
KM41C257P
KM41C257J
KM41C257Z
KM41C258P
KM41C258J
KM41C258Z
KM424C256Z
SIMM 30-pin
30-pin SIMM RAM
KM44C256bp
KM41C1000BJ
257J
KM44C256BZ
1K x4 static ram
30-pin simm memory "16m x 8"
|
PDF
|
128 k data sheet
Abstract: No abstract text available
Text: SECTION 3 MEMORY CONFIGURATION MOTOROLA DSP56304UM/AD 3-1 Memory Configuration 3.1 3.2 3.3 3.4 3.5 3.6 3-2 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 RAM CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
|
Original
|
DSP56304UM/AD
DSP56304
128 k data sheet
|
PDF
|
425dn
Abstract: DG28 dio8
Text: PRELIMINARY INFORMATION Semiconductors MV61903 1K x 9 PARITY FIFO The MV61903 is one of a new generation of RAM-based FIFOs designed for ease of use. The MV61903 features userprogrammable even or odd parity generation and checking circuitry, and an unencoded parity error flag.
|
OCR Scan
|
MV61903
MV61903
MV61903can
10MHz
MV61903s
20MHz
2200mW
425dn
DG28
dio8
|
PDF
|
Untitled
Abstract: No abstract text available
Text: PRELIMINARY INFORMATION Semiconductors MV61903 1K x 9 PARITY FIFO The MV61903 is one of a new generation of RAM-based FIFOs designed for ease of use. The MV61903 features userprogrammable even or odd parity generation and checking circuitry, and an unencoded parity error flag.
|
OCR Scan
|
MV61903
MV61903
10MHz
MV61903s
20MHz
2200mW
|
PDF
|
Untitled
Abstract: No abstract text available
Text: "PLESSEY SEMICONDUCTORS TS D Ê| 7ESDS13 ODOb?aS 7 2 2 0 5 1 3 P L E S S E Y SEMIC O N D U C T O R S fl 95D 06725 PLESSEY V T-ÿér2!T PRELIMINARY INFORMATION Semiconductors. M V 6 1 9 0 2 1K x 9 DIPSTICK" FIFO The MV61902 is one of a new generation of RAM-based
|
OCR Scan
|
7ESDS13
MV61902
10MHz
MV61902s
2200mW
|
PDF
|
em 513 diode
Abstract: H737
Text: PLESSEY SE MICO ND UC TO RS TS D E | 7S5DS13 D00t.7B4 T | 7 2 20513 P L E S S E Y S E M I C O N D U C T O R S 95D 06734 PLESSEY D PRELIMINARY INFORMATION S e m ic o n d u c to rs MV61903 y~ ' y < s ~ y s ' 1K X 9 PARITY FIFO The MV61903 is one of a new generation of RAM-based
|
OCR Scan
|
7S5DS13
MV61903
MV61903
2200mW
em 513 diode
H737
|
PDF
|
|
|
Static Random Access Memory SRAM
Abstract: F848 f840 F844 F84A F852 MC68F375 F85A
Text: SECTION 11 STATIC RANDOM ACCESS MEMORY SRAM 11.1 Introduction This SRAM module is a fast access (two clocks) general purpose 8K (8,192 bytes) static RAM (SRAM) for the MCU and is accessed via the IMB3. In addition there is 2K (configured as four blocks of 512 bytes each) of patch static RAM. These modules are
|
Original
|
512-byte
512byte
MC68F375
Static Random Access Memory SRAM
F848
f840
F844
F84A
F852
MC68F375
F85A
|
PDF
|
Untitled
Abstract: No abstract text available
Text: HIG H-SPEED 1K x 9 DUAL-PORT STATIC RAM W ITH BUSY ADVANCE INFORMATION IDT 7010 IDT 70104 FEATURES: DESCRIPTION: • High-speed access The IDT7010/IDT70104 are high-speed 1K X 9 dual port static RAMs. The IDT7010 Is designed to be used as a stand-alone 9-bit
|
OCR Scan
|
35/45/55/70ns
25/35/45/55ns
IDT7010/70104S
IDT7010/70104L
IDT7010
IDT70104
IDT7010/70104
48-pin
52-pin
|
PDF
|
ldr 6k
Abstract: MDT10P22 200H
Text: MDT10P22 BE 1. General Description This EPROM-Based 8-bit micro-controller uses a fully static CMOS design technology to achieve high speed, small size, low power and high noise immunity. On chip memory includes 1K words EPROM and80 bytes static RAM. Four comparator inputs with external Vref
|
Original
|
MDT10P22
and80
14-bit
MDT10P22
ldr 6k
200H
|
PDF
|
MV61902DG
Abstract: MV61902DP MV66030 MV66401
Text: A PSem LEiconductors SSEY• W PRELIMINARY INFORMATION MV61902 1K x 9 DIPSTICK" FIFO The MV61902 is one of a new generation o f RAM-based FIFOs designed fo r ease of use. The MV61902 has a userprogrammable flag DIPSTICK w hich defaults to a conventional ‘half-full’ flag on power-up.
|
OCR Scan
|
MV61902
MV61902
10MHz
MV61902s
20MHz
2200mW
MV61902DG
MV61902DP
MV66030
MV66401
|
PDF
|
EMP116MGAW-70E
Abstract: EMP116MGAW 3.3v 1Mx16 static ram high speed
Text: Preliminary EMP116MGAW Series 1Mx16 Pseudo Static RAM Document Title 1M x 16 bit Pseudo SRAM EMP116MGAW Series Specification Revision History Revision No. History Draft Date Remark 0.0 Initial Draft Oct. 24 , 2005 Preliminary Emerging Memory & Logic Solutions Inc.
|
Original
|
EMP116MGAW
1Mx16
200us
200us
EMP116MGAW-70E
3.3v 1Mx16 static ram high speed
|
PDF
|
KMCJ532512
Abstract: KM23C1000-20 KM28C64B KMM594 KM718B90-12 zip 40pin 30-pin simm memory "16m x 8" KM41C4000C-6 KM41C16000ALL KM48V2104AL
Text: FUNCTION GUIDE MEMORY ICs 1. 1.1 INTRODUCTION Dynamic RAM KM41C1000C-6 1Mx1 KM41C1000CL-6 KM41C1000CSL-6 25 6Kx4 KM44C256C-6 KM44C256CL-6 KM44C256CSL-6 4Mbit— 4Mx1 T KM41C4000C-5 — KM41C4000C-6 KM41C4000C-7 KM41C4000C-8 KM41C4000CL-5 KM41C4000CL-6 KM41C4000CL-7
|
OCR Scan
|
KM41C1000C-6
KM41C1000CL-6
KM41C1000CSL-6
KM44C256C-6
KM44C256CL-6
KM44C256CSL-6
KM41C4000C-5
KM41C4000C-6
KM41C4000C-7
KM41C4000C-8
KMCJ532512
KM23C1000-20
KM28C64B
KMM594
KM718B90-12
zip 40pin
30-pin simm memory "16m x 8"
KM41C4000C-6
KM41C16000ALL
KM48V2104AL
|
PDF
|
kjd1
Abstract: t17c marking T18C UT63M125 application notes 1553B F801 UT1553B T16B 3F6 smd smd 3F9
Text: UT1553B RTR Remote Terminal with RAM FEATURES ❐ Complete MIL-STD-1553B remote terminal interface ❐ 1K x 16 of on-chip static RAM for message data, completely accessible to host ❐ Self-test capability, including continuous loop-back ❐ ❐ ❐ ❐ MCSA 4:0
|
Original
|
UT1553B
MIL-STD-1553B
5962-8957601XC)
kjd1
t17c
marking T18C
UT63M125 application notes
1553B
F801
T16B
3F6 smd
smd 3F9
|
PDF
|
EMP216MAAW
Abstract: EMP216MAAW-70E
Text: Preliminary EMP216MAAW Series 2Mx16 Pseudo Static RAM Document Title 2M x 16 bit Pseudo SRAM EMP216MAAW Series Specification Revision History Revision No. History Draft Date Remark 0.0 Initial Draft Oct. 24 , 2005 Preliminary Emerging Memory & Logic Solutions Inc.
|
Original
|
EMP216MAAW
2Mx16
200us
200us
EMP216MAAW-70E
|
PDF
|
1553B
Abstract: F801 UT1553B 63M125 1553b rti t17c
Text: UT1553B RTR Remote Terminal with RAM FEATURES ❐ Complete MIL-STD-1553B remote terminal interface ❐ 1K x 16 of on-chip static RAM for message data, completely accessible to host ❐ Self-test capability, including continuous loop-back ❐ ❐ ❐ ❐ MCSA 4:0
|
Original
|
UT1553B
MIL-STD-1553B
MIL-M-38510.
36-Lead
Packaging-10
XLN-589
24-Lead
Packaging-11
1553B
F801
63M125
1553b rti
t17c
|
PDF
|
000-3FF
Abstract: 200H MDT1010
Text: MDT1010 1. General Description This ROM-Based 8-bit micro-controller uses a fully static CMOS design technology combines higher speed and smaller size with the low power and high noise immunity of CMOS. On chip memory system includes 1.0 K bytes of ROM, and 32 bytes of static RAM.
|
Original
|
MDT1010
14-bit
000-3FF
200H
MDT1010
|
PDF
|
