ramps 1.4
Abstract: CY24126 CY24126SC lcd 3901 PLL 2400 MHZ
Text: PRELIMINARY CY24126 MediaClock for LCD Projectors 1CY2295 Features Benefits • Integrated phase-locked loop High-performance PLL tailored for projector applications • Low jitter, high accuracy outputs Meets critical timing requirements in complex system designs
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CY24126
1CY2295
Hz/120
CY24126
ramps 1.4
CY24126SC
lcd 3901
PLL 2400 MHZ
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CY28316
Abstract: CY28317-2 CY28317PVC-2 CY28317PVC-2T CY28317ZC-2 CY28317ZC-2T ILB1206 PLE133T 1CY2
Text: CY28317-2 FTG for Mobile VIA PL133T and PLE133T Chipsets 1CY28317-2 Features • Single-chip system frequency synthesizer for mobile VIA PL133T and PLE133T chipsets • Programmable clock output frequency with less than 1 MHz increment • Vendor ID and Revision ID support
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CY28317-2
PL133T
PLE133T
1CY28317-2
48-pin
CY28316
CY28317-2
CY28317PVC-2
CY28317PVC-2T
CY28317ZC-2
CY28317ZC-2T
ILB1206
1CY2
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CY28316
Abstract: ILB1206 PLE133T
Text: 1CY28316 CY28316: 12/00 Revision: March 28, 2001 PRELIMINARY CY28316 FTG for VIA PL133T and PLE133T Features • Single-chip system frequency synthesizer for VIA PL133T and PLE133T chipsets • Programmable clock output frequency with less than 1 MHz increment
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1CY28316
CY28316:
CY28316
PL133T
PLE133T
PLE133T
CY28316
ILB1206
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23S08
Abstract: CY2308 CY23S08 REF05
Text: 1CY23S08 CY23S08 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see Table 2 • Multiple low-skew outputs — Output-output skew less than 200 ps — Device-device skew less than 700 ps
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1CY23S08
CY23S08
10-MHz
133-MHz
16-pin
150-mil
CY23S08
23S08
CY2308
REF05
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PDF
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CY2213
Abstract: CY2213ZC-1 CY2213ZC-1T CY2213ZC-2 CY2213ZC-2T
Text: CY2213 High-Frequency Programmable PECL Clock Generator 1CY2213 Features Benefits • Jitter peak-peak TYPICAL = 35 ps High-accuracy clock generation • LVPECL output One pair of differential output drivers • Default Select option Phase-locked loop (PLL) multiplier select
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CY2213
1CY2213
16-pin
400-MHz
500-MHz
200-MHz
CY2213
CY2213ZC-1
CY2213ZC-1T
CY2213ZC-2
CY2213ZC-2T
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PDF
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CY28159
Abstract: CY28159PVC CY28159PVCT CY28159ZC CY28159ZCT ILB1206 dmg cpu
Text: 1CY28159 CY28159 Clock Generator for Serverworks Grand Champion Chipset Applications Features • • • • • All outputs compliant with Intel specifications • External resistor for current reference • Selection logic for differential swing control, test mode,
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1CY28159
CY28159
48-pin
31818-MHz
48-MHz
CY28159
CY28159PVC
CY28159PVCT
CY28159ZC
CY28159ZCT
ILB1206
dmg cpu
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PDF
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AMD 700 chipset
Abstract: AMD-750 CY22K7 CY22K7PVC-1
Text: THIS SPEC IS OBSOLETE Spec No: 38-07333 Spec Title: CY22K7 133-MHz Spread Spectrum Clock Generator For Use With the AMD-K7 Processor and AMD-750 Chipset Sunset Owner: Rose Galindez RGL Replaced by: None [+] Feedback 1CY22K7 CY22K7 133-MHz Spread Spectrum Clock Generator For Use With
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CY22K7
133-MHz
AMD-750
1CY22K7
CY22K7
AMD-750
AMD 700 chipset
CY22K7PVC-1
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PDF
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ansi-y14.5m-1982
Abstract: No abstract text available
Text: 1CY2310NZCY2310 NZCY2313BNZ CY2313BNZ 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Features Functional Description • One input to 13 output buffer/driver • Supports up to three SDRAM DIMMs • One additional outputs for feedback • SMBus interface for output control
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1CY2310NZCY2310
NZCY2313BNZ
CY2313BNZ
28-pin
300-mil)
CY2313BNZ
10uctor
ansi-y14.5m-1982
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Signal Path Designer
Abstract: No abstract text available
Text: 1CY2509/10 CY2509/10 Spread Aware , Ten/Eleven Output Zero Delay Buffer Features Key Specifications • Spread AwareTM—designed to work with SSFTG reference signals • Well suited to both 100- and 133-MHz designs • Ten CY2509 or eleven (CY2510) LVCMOS/LVTTL
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1CY2509/10
CY2509/10
133-MHz
CY2509)
CY2510)
CY2510
CY2509
24-pin
W132-09B/10B
Signal Path Designer
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PDF
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Untitled
Abstract: No abstract text available
Text: 1CY2303 CY2303 Phase-Aligned System Clock Features Benefits • 3-multiplier configuration 1x, 2x, 4x Ref • Single phase-locked loop architecture 10 MHz to 166.67 MHz operating range reference input from 10 MHz to 41.67 MHz • Phase Alignment All outputs will have a consistent phase relationship with each
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1CY2303
CY2303
150-mil
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CY26187-1
Abstract: No abstract text available
Text: CY26187-1 PRELIMINARY Broadcom Reference Design Clock Generator 2CY26187-1-1CY2295 Features Benefits • Integrated phase-locked loop Highest performance PLL tailored for multimedia applications • Low skew, low jitter, high accuracy outputs Meets critical timing requirements in complex system designs
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CY26187-1
2CY26187-1-1CY2295
SDK5680
CY26187-1
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CY2309NZ
Abstract: CY2309NZSI-1H
Text: 1CY2309NZ CY2309NZ Nine Output, 3.3V Buffer Features Functional Description • One input to nine output buffer/driver • Supports two DIMMs or four SO-DIMMs with one additional output for feedback to an external or chipset PLL • Low power consumption for mobile applications
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1CY2309NZ
CY2309NZ
16-pin
150-mil
CY2309NZ
CY2309NZSI-1H
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CY2308SXC-1
Abstract: CY2308SXI-1H CY2308 CY2308SI-XX CY2308SXI
Text: 1CY2308 CY2308 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see “Available CY2308 Configurations” table • Multiple low-skew outputs — Output-output skew less than 200 ps
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1CY2308
CY2308
10-MHz
133-MHz
16-pin
150-mil
16-pin
CY2308
CY2308SXC-1
CY2308SXI-1H
CY2308SI-XX
CY2308SXI
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PDF
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Untitled
Abstract: No abstract text available
Text: CY28159 Clock Generator for Serverworks Grand Champion Chipset Applications 1CY28159 Features • Eight differential CPU clock outputs • All outputs compliant with Intel specifications • One PCI output • External resistor for current reference • One 14.31818 MHz reference clock
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CY28159
1CY28159
200MHz
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Untitled
Abstract: No abstract text available
Text: 1CY2254A CY2254A Pentium Processor Compatible Clock Synthesizer/Driver Features • Freq. stability = 0.01% max. • Multiple clock outputs to meet requirements of most Pentium® motherboards — Four pin-selectable CPU clocks @ 66.66 MHz, 60.0 MHz, and 50.0 MHz for support of Intel Triton PCIset
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1CY2254A
CY2254A
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Untitled
Abstract: No abstract text available
Text: CY22150F PRELIMINARY One-PLL General Purpose FLASH Programmable and 2-Wire Serially Programmable Clock Generator 1CY2295 Features Benefits • Integrated phase-locked loop PLL Internal PLL to generate 6 outputs up to 200 MHz. Able to generate custom frequencies from an external crystal or a driven source.
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CY22150F
1CY2295
CY22150F
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Untitled
Abstract: No abstract text available
Text: 1CY2220 CY2220 133-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs Features Benefits • Compliant to Intel CK00 Clock Synthesizer/Driver Specifications Supports next generation Pentium® processors using differential clock drivers
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1CY2220
CY2220
133-MHz
48-MHz
56-pin
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REF05
Abstract: No abstract text available
Text: 1CY2308 CY2308 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see “Available CY2308 Configurations” table • Multiple low-skew outputs — Output-output skew less than 200 ps
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1CY2308
CY2308
CY2308
10-MHz
133-MHz
16-pin
150-mil
REF05
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PDF
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ILB1206
Abstract: CY28159 CY28159PVC CY28159PVCT CPU44
Text: CY28159 Clock Generator for Serverworks Grand Champion Chipset Applications 1CY28159 Features • Eight differential CPU clock outputs • All outputs compliant with Intel specifications • One PCI output • External resistor for current reference • One 14.31818 MHz reference clock
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CY28159
1CY28159
48-pin
ILB1206
CY28159
CY28159PVC
CY28159PVCT
CPU44
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PDF
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CY2280
Abstract: CY2281 CY2313ANZ NZCY2313ANZ
Text: 1CY2310NZCY2310 NZCY2313ANZ CY2313ANZ 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Features Functional Description • One input to 13 output buffer/driver • Supports up to three SDRAM DIMMs • One additional outputs for feedback • Serial interface for output control
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1CY2310NZCY2310
NZCY2313ANZ
CY2313ANZ
100-MHz
28-pin
300-mil)
CY2313ANZ
CY2280
CY2281
NZCY2313ANZ
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PDF
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Untitled
Abstract: No abstract text available
Text: 1CY2303 CY2303 Phase-Aligned Clock Multiplier Features Benefits • 3-multiplier configuration 1x, 2x, 4x Ref • Single phase-locked loop architecture 10 MHz to 166.67 MHz operating range reference input from 10 MHz to 41.67 MHz • Phase Alignment All outputs will have a consistent phase relationship with each
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1CY2303
CY2303
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PDF
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CY28316
Abstract: CY28317 ILB1206 PLE133T
Text: PRELIMINARY CY28317 FTG for Mobile VIA PL133T and PLE133T Chipsets 1CY28317 Features • Single-chip system frequency synthesizer for mobile VIA PL133T and PLE133T chipsets • Programmable clock output frequency with less than 1 MHz increment • Integrated fail-safe Watchdog Timer for system recovery
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CY28317
PL133T
PLE133T
1CY28317
CY28316
CY28317
ILB1206
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PDF
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Untitled
Abstract: No abstract text available
Text: 1CY2210 CY2210 133 MHz Spread Spectrum Clock Synthesizer/Driver with AGP, USB, and DRCG Support Features Benefits Usable with Pentium II and Pentium® III processors • Mixed 2.5V and 3.3V Operation • Compliant to Intel® CK133 CY2210-3 & CK133W (CY2210-2) synthesizer and driver specification
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1CY2210
CY2210
CK133
CY2210-3)
CK133W
CY2210-2)
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CY28316
Abstract: CY28317-2 CY28317PVC-2 CY28317PVC-2T CY28317ZC-2 CY28317ZC-2T ILB1206 PLE133T
Text: CY28317-2 FTG for Mobile VIA PL133T and PLE133T Chipsets 1CY28317-2 Features • Single-chip system frequency synthesizer for mobile VIA PL133T and PLE133T chipsets • Programmable clock output frequency with less than 1 MHz increment • Vendor ID and Revision ID support
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CY28317-2
PL133T
PLE133T
1CY28317-2
48-pin
CY28316
CY28317-2
CY28317PVC-2
CY28317PVC-2T
CY28317ZC-2
CY28317ZC-2T
ILB1206
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PDF
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