54SX32
Abstract: A54SX32 A54SX32A A54SX72A PAR64 REQ64 54SX32A il 074
Text: Preliminary v1.0 HiRel SX-A Family FPGAs Le a di n g E d ge P er f o r m a n ce • QML Certified Devices • 215 MHz System Performance Military Temperature • 100% Military Temperature Tested (–55°C and +125°C) • 5.3ns Clock-to-Out (Pin-to-Pin) (Military Temperature)
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HiRel a54sx72a unused
Abstract: No abstract text available
Text: Advanced v1.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10
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RT54SX-S
RT54SX-S
TM1019
HiRel a54sx72a unused
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rt54sx32su
Abstract: RTSX72 RTSX32SU RTSX72-S
Text: Advanced v0.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
rt54sx32su
RTSX72
RTSX32SU
RTSX72-S
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Pin Compatibility Allows Prototyping with Commercial SX-A FPGAs
Abstract: RT54SX72S-CQ256 RTSX32S
Text: Advanced v 0.1.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <
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RT54SX-S
100krad
RT54SX-S
Pin Compatibility Allows Prototyping with Commercial SX-A FPGAs
RT54SX72S-CQ256
RTSX32S
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Untitled
Abstract: No abstract text available
Text: v2 . 1 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
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sx08a
Abstract: No abstract text available
Text: v4.0 SX-A Family FPGAs u e Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5V PCI, 5V TTL, 3.3V LVTTL, 2.5V LVCMOS2 • 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input Tolerance and 5V Drive Strength • Devices Support Multiple Temperature Grades
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TM101
Abstract: No abstract text available
Text: Advanced v1.2.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate < 10–10
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RT54SX-S
100krad
RT54SX-S
TM1019
TM101
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RTSX32su
Abstract: Actel a54sx72a tid Silicon Sculptor II
Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RTSX32su
Actel a54sx72a tid
Silicon Sculptor II
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A54SX16A
Abstract: No abstract text available
Text: v4.0 SX-A Family FPGAs u e Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5V PCI, 5V TTL, 3.3V LVTTL, 2.5V LVCMOS2 • 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input Tolerance and 5V Drive Strength • Devices Support Multiple Temperature Grades
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HiRel a54sx72a unused
Abstract: No abstract text available
Text: Advanced v1.6 RTSX-S RadTolerant FPGAs for Space Application S p ec i a l F e a tu r es fo r S p ac e • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10
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TM1019
HiRel a54sx72a unused
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RTSX32su
Abstract: RTSX32SU CQ84 RTSX72SU
Text: v2.0 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RTSX32su
RTSX32SU CQ84
RTSX72SU
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Untitled
Abstract: No abstract text available
Text: Advanced v0.1.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <
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RT54SX-S
100krad
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A54SX32A
Abstract: A54SX72A PAR64 REQ64 RT54SX-S
Text: Advanced v1.2 HiRel SX-A Family FPGAs L ea d i n g E dg e P e rf o rm an c e • Cold-Sparing Capability • 215 MHz System Performance Military Temperature • Slow Slew Rate Option • 5.3 ns Clock-to-Out (Pin-to-Pin) (Military Temperature) • QML Certified Devices
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A54SX72* radiation
Abstract: cg624 A54SX72A actel 1020 datasheet RT54SX72S RT54SX-S TM1019 HiRel a54sx72a unused
Text: Advanced v1.4 RT54SX-S RadTolerant FPGAs for Space Applications S p ec i a l F e a tu r es fo r S p ac e • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10
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RT54SX-S
TM1019
A54SX72* radiation
cg624
A54SX72A
actel 1020 datasheet
RT54SX72S
RT54SX-S
HiRel a54sx72a unused
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54SX72
Abstract: A54SX32APQ FBGA-484 A54SX16A THERMAL Fuse m20 tf 115 c PAR64 REQ64 A54SX08A A54SX16 A54SX32A
Text: Preliminary v1.1 SX-A Family FPGAs Leading Edge Performance • Configurable I/O Support for 3.3V/5.0V PCI, LVTTL, and TTL • Configurable Weak Resistor Pullup or Pulldown for Tri-Stated Outputs at Power Up • 250 MHz System Performance • 4ns Clock-to-Out Pin-to-Pin
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RTSX32
Abstract: voter PAR64 REQ64 RT54SX72S RT54SX-S TM1019 Cqfp256
Text: Advanced v0.2 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <
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RT54SX-S
100krad
RTSX32
voter
PAR64
REQ64
RT54SX72S
RT54SX-S
TM1019
Cqfp256
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22B2 DIODE
Abstract: RTSX-S datasheet SX FPGAs A54SX08A A54SX16A A54SX32A A54SX72A PQ208 TQ100 TQ144
Text: v5.1 SX-A Family FPGAs Leading-Edge Performance • • • 250 MHz System Performance 350 MHz Internal Performance • • • Specifications • • • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops
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RTSX32SU
Abstract: RTSX32 PQFP die size C5249 bst r16 166 P790 actel 1020 datasheet A54SX72A CC256 CQ208
Text: Advanced v0.3 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RTSX32SU
RTSX32
PQFP die size
C5249
bst r16 166
P790
actel 1020 datasheet
A54SX72A
CC256
CQ208
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A54SX72A
Abstract: A54SX08A A54SX16A A54SX32A RT54SX72S RT54SX-S
Text: v2.2 SX-A Automotive Family FPGAs Specifications • 12,000 to 108,000 Available System Gates • Up to 360 User-Programmable I/O Pins • Up to 2,012 Dedicated Flip-Flops • 0.22µ CMOS Process Technology Features u e • Nonvolatile • Configurable I/O Support for 3.3V PCI, 3.3V LVTTL,
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RTSX72
Abstract: RTSX72SU A54SX72A TID "tristate buffer" A54SX32S-PQ208 RT54SXproto
Text: Advanced v0.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RTSX72
RTSX72SU
A54SX72A TID
"tristate buffer"
A54SX32S-PQ208
RT54SXproto
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A54SX16A
Abstract: No abstract text available
Text: v2.0 SX-A Automotive Family FPGAs Specifications • 12,000 to 108,000 Available System Gates • Up to 360 User-Programmable I/O Pins • Up to 2,012 Dedicated Flip-Flops • 0.22µ CMOS Process Technology Features u e • Nonvolatile • Configurable I/O Support for 3.3V PCI, 3.3V LVTTL,
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54SX72
Abstract: FBGA-484 A54SX32APQ208 A54SX16A
Text: Preliminary v1.1 SX-A Family FPGAs Leading Edge Performance • Configurable I/O Support for 3.3V/5.0V PCI, LVTTL, and TTL • Configurable Weak Resistor Pullup or Pulldown for Tri-Stated Outputs at Power Up • 250 MHz System Performance • 4ns Clock-to-Out Pin-to-Pin
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VeriBes24
54SX72
FBGA-484
A54SX32APQ208
A54SX16A
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SU 177
Abstract: RTSX32SU A54SX72* radiation Actel a54sx72a tid antifuse A54SX72A CC256 CG624 CQ208 CQ256
Text: Advanced v0.3 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
SU 177
RTSX32SU
A54SX72* radiation
Actel a54sx72a tid
antifuse
A54SX72A
CC256
CG624
CQ208
CQ256
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RT54SX72SCQ208
Abstract: Actel a54sx72a tid RT54SX72S matsua fuse resistor PQFP die size actel 1020 datasheet ACTEL CCGA 624 mechanical antifuse A54SX72A CC256
Text: v2 . 2 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RT54SX72SCQ208
Actel a54sx72a tid
RT54SX72S
matsua fuse resistor
PQFP die size
actel 1020 datasheet
ACTEL CCGA 624 mechanical
antifuse
A54SX72A
CC256
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