IS43DR83200A
Abstract: IS43DR16160A-3DBLI datasheet IS43DR16160A-37CBLI IS43DR83200A-37CBLI IS43DR32160A DDR2 x32
Text: IS43DR83200A IS43/46DR16160A, IS43DR32160A 32Mx8, 16Mx16, 16Mx32 stacked die DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle
|
Original
|
IS43DR83200A
IS43/46DR16160A,
IS43DR32160A
32Mx8,
16Mx16,
16Mx32
18-compatible)
IS43DR32160A-37CBLI
400Mhz
IS43DR32160A-5BBLI
IS43DR83200A
IS43DR16160A-3DBLI datasheet
IS43DR16160A-37CBLI
IS43DR83200A-37CBLI
IS43DR32160A
DDR2 x32
|
PDF
|
IS42S16320D-7TLI
Abstract: IS42S16320D is42s16320 IS42S16320D-7BL IS42S86400D-7TL IS42S16320D-7TL IS45S16320D-7TLA1 IS42S16320D-5TL IS45S16320D-7TLA2 is42s86400
Text: IS42/45R86400D/16320D/32160D IS42/45S86400D/16320D/32160D 16Mx32, 32Mx16, 64Mx8 PRELIMINARY INFORMATION JUNE 2011 512Mb SDRAM FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge
|
Original
|
IS42/45R86400D/16320D/32160D
IS42/45S86400D/16320D/32160D
16Mx32,
32Mx16,
64Mx8
512Mb
IS42/45SxxxxxD
IS42/45RxxxxxD
IS42/45R86400D/16320D/32160D,
IS42S16320D-7TLI
IS42S16320D
is42s16320
IS42S16320D-7BL
IS42S86400D-7TL
IS42S16320D-7TL
IS45S16320D-7TLA1
IS42S16320D-5TL
IS45S16320D-7TLA2
is42s86400
|
PDF
|
HSD16M32D4
Abstract: HSD16M32D4-10 HSD16M32D4-10L HSD16M32D4-12
Text: HANBit HSD16M32D4 Synchronous DRAM Module 64Mbyte 16Mx32-Bit , 100pin DIMM, 4Banks, 8K Ref., 3.3V Part No. HSD16M32D4 GENERAL DESCRIPTION The HSD16M32D4 is a 16M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists of four CMOS 2M x 16 bit x 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 100-pin glass-epoxy substrate.
|
Original
|
HSD16M32D4
64Mbyte
16Mx32-Bit)
100pin
HSD16M32D4
400mil
100-pin
HSD16M32D4-10
HSD16M32D4-10L
HSD16M32D4-12
|
PDF
|
IS42S32160C
Abstract: 42S32160C is42s32160 IS42S32160C-75BLI
Text: IS42S32160C 16Mx32 512Mb SYNCHRONOUS DRAM DESCRIPTION: FEATURES: • • • • • • • • Clock frequency: 166, 133 MHz Fully synchronous operation Internal pipelined architecture Programmable Mode – CAS# Latency: 2 or 3 – Burst Length: 1, 2, 4, 8, or full page
|
Original
|
IS42S32160C
16Mx32
512Mb
IS42S32160C
IS42S32160C-75BL
IS42S32160C-6BL
8x13mm
42S32160C
is42s32160
IS42S32160C-75BLI
|
PDF
|
Untitled
Abstract: No abstract text available
Text: WED3DL3216V White Electronic Designs PRELIMINARY 16Mx32 SDRAM FEATURES DESCRIPTION The WED3DL3216V is an 16Mx32 Synchronous DRAM configured as 4x4Mx32. The SDRAM BGA is constructed with two 16Mx16 SDRAM die mounted on a multi-layer laminate substrate and packaged in a 119 lead, 17mm
|
Original
|
WED3DL3216V
16Mx32
WED3DL3216V
4x4Mx32.
16Mx16
133MHz,
125MHz,
100MHz.
|
PDF
|
16MX32
Abstract: IS42RM32160C
Text: IS42SM32160C IS42RM32160C 16Mx32 512Mb Mobile Synchronous DRAM FEATURES: • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access and precharge • Programmable CAS latency: 2, 3 • Programmable Burst Length: 1, 2, 4, 8, and Full
|
Original
|
IS42SM32160C
IS42RM32160C
16Mx32
512Mb
IS42SM/RM32160C
IS42SM32160C-7BLI
IS42SM32160C-75EBLI
8x13mm
IS42RM32160C
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 512MBit MOBILE SDR SDRAMs based on 4M x 4Bank x32 I/O Specification of 512M 16Mx32bit Mobile SDRAM Memory Cell Array - Organized as 4banks of 4,194,304 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
|
Original
|
512MBit
16Mx32bit)
11Preliminary
512Mbit
32bits
200us
|
PDF
|
sc413
Abstract: BC163 quanta GND194 g7001 G71M-U AK-34 DDR3 Infineon quanta computer Quanta AT8
Text: 5 4 3 2 CH-A NVIDIA PCI-E x16 D G71M G71M-U CH-B FCBGA 1148pin TV CH-C C CRT MXM CONNECTOR 1 VRAM GDDR3 8Mx32 16Mx32 D VRAM GDDR3 8Mx32 16Mx32 VRAM C GDDR3 8Mx32 16Mx32 LVDS CH-D VRAM GDDR3 8Mx32 16Mx32 2.5V B B 3.3V A VIN VCORE VRM VIN 1.8V VRM VCORE A 1.8V
|
Original
|
8Mx32
16Mx32
G71M-U
1148pin
sc413
BC163
quanta
GND194
g7001
G71M-U
AK-34
DDR3 Infineon
quanta computer
Quanta AT8
|
PDF
|
RFU20
Abstract: G72M sc413 BLM18PG181SN1D nvidia g72m 7SH02 nvidia MXM MXM CONNECTOR G72M-V quanta computer
Text: 5 4 D 3 2 CH-A NVIDIA PCI-E x16 CH-B FCBGA 820pin MXM CONNECTOR D VRAM GDDR3 8Mx32 16Mx32 Page8 Channel C is available on G73M only CRT C VRAM GDDR3 8Mx32 16Mx32 Page7 G72M G73M TV 1 C LVDS Page3 ~ 6 2.5V B B 3.3V Page2 VIN VCORE VRM VCORE 1.8V VRM 1.8V Page9
|
Original
|
8Mx32
16Mx32
820pin
NONPHY-X16
FG-13X91-20-230P
H-C236D118P2
RFU20
G72M
sc413
BLM18PG181SN1D
nvidia g72m
7SH02
nvidia MXM
MXM CONNECTOR
G72M-V
quanta computer
|
PDF
|
H55S5132DFR
Abstract: H55S5122 h55s512 RA13 mobile MOTHERBOARD CIRCUIT diagram H55S5122DFR
Text: 512MBit MOBILE SDR SDRAMs based on 4M x 4Bank x32 I/O Specification of 512M 16Mx32bit Mobile SDRAM Memory Cell Array - Organized as 4banks of 4,194,304 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
|
Original
|
512MBit
16Mx32bit)
512Mbit
H55S5122DFR
H55S5132DFR
32bits
200us
H55S5122
h55s512
RA13
mobile MOTHERBOARD CIRCUIT diagram
|
PDF
|
samsung CL21
Abstract: K4X51323PE CL21 CL31 DDR266 DDR333
Text: K4X51323PE - 7 8 E/G Mobile DDR SDRAM 16Mx32 Mobile DDR SDRAM 1. FEATURES • VDD/VDDQ = 1.8V/1.8V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK)
|
Original
|
K4X51323PE
16Mx32
samsung CL21
CL21
CL31
DDR266
DDR333
|
PDF
|
hy5rs123235b
Abstract: HY5RS123235BFP HY5RS123235
Text: HY5RS123235BFP 512Mbit 16Mx32 GDDR3 SDRAM HY5RS123235BFP This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied.
|
Original
|
HY5RS123235BFP
512Mbit
16Mx32)
HY5RS123235BFP
hy5rs123235b
HY5RS123235
|
PDF
|
DIMM 100 Pin
Abstract: 32174ASQM4G09T
Text: 16M x 32 Bit 100 PIN SDRAM DIMM 100 PIN SYNCHRONOUS DRAM DIMM 32174ASQM4G09T 100 Pin 16Mx32 SDRAM DIMM Unbuffered, 4k Refresh, 3.3V with SPD General Description Pin Assignment Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side 1 Vss 51 Vss 26 Vss
|
Original
|
32174ASQM4G09T
16Mx32
DS623-0
DIMM 100 Pin
|
PDF
|
321606-S54T15TD
Abstract: No abstract text available
Text: 16M x 32 Bit 5V FPM SIMM Fast Page Mode FPM DRAM SIMM 321606-S54T15TD 72 Pin 16Mx32 FPM SIMM Unbuffered, 4k Refresh, 5V Pin Assignment General Description Pin # Symbol 1 Vss 2 DQ0 3 DQ18 4 DQ1 5 DQ19 6 DQ2 7 DQ20 8 DQ3 9 DQ21 10 Vcc 11 PD5 12 A0 13 A1 14
|
Original
|
321606-S54T15TD
16Mx32
16Mx4
DS512
|
PDF
|
|
HY5DU113222FM
Abstract: No abstract text available
Text: HY5DU113222FM P 512M(16Mx32) GDDR SDRAM HY5DU113222FM(P) This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied.
|
Original
|
HY5DU113222FM
16Mx32)
912-bit
256Mbit
144ball
|
PDF
|
Untitled
Abstract: No abstract text available
Text: HANBit HMD16M32M8EH 64Mbyte 16Mx32 72-pin EDO Mode 4K Ref. SIMM Design 5V Part No. HMD16M32M8EH GENERAL DESCRIPTION The HMD16M32M8EH is a 16M x 32bit dynamic RAM high-density memory module. The module consists of eight CMOS 16M x 4bit DRAMs in 32-pin TSOPII packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A
|
Original
|
HMD16M32M8EH
64Mbyte
16Mx32)
72-pin
HMD16M32M8EH
32bit
32-pin
72-pin,
|
PDF
|
HY5S7B2ALFP
Abstract: RA12
Text: 512MBit MOBILE SDR SDRAMs based on 4M x 4Bank x32 I/O Specification of 512M 16Mx32bit Mobile SDRAM Memory Cell Array - Organized as 4banks of 4,194,304 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
|
Original
|
512MBit
16Mx32bit)
512Mbit
32bits
200us
HY5S7B2ALFP
RA12
|
PDF
|
IS42VM32160C
Abstract: No abstract text available
Text: IS42VM32160C 16Mx32 512Mb Mobile Synchronous DRAM FEATURES: • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access and precharge • Programmable CAS latency: 2, 3 • Programmable Burst Length: 1, 2, 4, 8, and Full
|
Original
|
IS42VM32160C
16Mx32
512Mb
IS42VM32160C
IS42VM32160C-75BL
8x13mm
IS42VM32160C-75BLI
IS42VM32160C-75BI
IS42VM32160C-10BLI
|
PDF
|
Untitled
Abstract: No abstract text available
Text: IS43/46DR32160C 16Mx32 512Mb DDR2 DRAM FEATURES ADVANCED INFORMATION OCTOBER 2010 DESCRIPTION • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O SSTL_18-compatible • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS)
|
Original
|
IS43/46DR32160C
16Mx32
512Mb
18-compatible)
-40oC
DDR2-400B
IS46DR32160C-5BBLA1
|
PDF
|
is42s32160
Abstract: No abstract text available
Text: IS42S32160C 16Mx32 512Mb SYNCHRONOUS DRAM DESCRIPTION: FEATURES: • • • • • • • • Clock frequency: 166, 133 MHz Fully synchronous operation Internal pipelined architecture Programmable Mode – CAS# Latency: 2 or 3 – Burst Length: 1, 2, 4, 8, or full page
|
Original
|
IS42S32160C
16Mx32
512Mb
IS42S32160C
90-Ball)
is42s32160
|
PDF
|
Untitled
Abstract: No abstract text available
Text: IS43/46R86400D IS43/46R16320D, IS43/46R32160D PRELIMINARY INFORMATION 16Mx32, 32Mx16, 64Mx8 FEBRUARY 2011 512Mb DDR SDRAM FEATURES DEVICE OVERVIEW • • • • ISSI’s 512-Mbit DDR SDRAM achieves high speed data transfer using pipeline architecture and two data word
|
Original
|
IS43/46R86400D
IS43/46R16320D,
IS43/46R32160D
16Mx32,
32Mx16,
64Mx8
512Mb
|
PDF
|
Untitled
Abstract: No abstract text available
Text: SU5321635D8F6CU August 18, 2004 Ordering Information Part Numbers Description Module Speed SM5321635D8F6CG 16Mx32 64MB , DDR, 100-pin DIMM, Unbuffered, Non-ECC, 16Mx16 Based, DDR266A, 25.40mm, 22Ω DQ termination. PC2100 @ CL 2.0, 2.5 SB5321635D8F6CG 16Mx32 (64MB), DDR, 100-pin DIMM, Unbuffered, Non-ECC,
|
Original
|
SU5321635D8F6CU
SM5321635D8F6CG
SB5321635D8F6CG
16Mx32
100-pin
16Mx16
DDR266A,
|
PDF
|
SM532168574F03R
Abstract: No abstract text available
Text: SM532168574F03R August 28, 2002 Ordering Information Part Numbers SM532168574F03R Description 16Mx32 64MB , SDRAM 100-pin DIMM, Unbuffered 16Mx8 Based, PC133, CL3, 29.72mm Revision History • August 28, 2002 Datasheet released. Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
|
Original
|
SM532168574F03R
SM532168574F03R
16Mx32
100-pin
16Mx8
PC133,
64MByte
16Mx32)
|
PDF
|
Untitled
Abstract: No abstract text available
Text: DRAM MODULE KMM53216004BK/BKG 4 Byte 16Mx32SIMM 16Mx4 base Revision 0.0 Sept. 1997 DRAM MODULE KMM53216004BK/BKG Revision History Version 0.0 (Sept, 1997) • Removed two AC parameters t CACP(access time from CAS) and tAAP(access time from col. addr.) in A C CHARACTERISTICS.
|
OCR Scan
|
KMM53216004BK/BKG
16Mx32SIMM
16Mx4
KMM53216004BK/BKG
16Mx4,
KMM53216004B
16Mx32bits
|
PDF
|