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    16 BIT REGISTER VHDL Search Results

    16 BIT REGISTER VHDL Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SF-10GSFPPLCL-000 Amphenol Cables on Demand Amphenol SF-10GSFPPLCL-000 SFP+ Optical Module - 10GBASE-SR (up to 300m/984') SFP+ Multimode Optical Transceiver Module (Duplex LC Connectors) - Cisco & HP Compatible Datasheet
    SF-XP85B102DX-000 Amphenol Cables on Demand Amphenol SF-XP85B102DX-000 SFP28 25GBASE-SR Short-Range 850nm Multi-Mode Optical Transceiver Module (Duplex LC Connector) by Amphenol XGIGA [XP85B102DX] Datasheet
    SF-QXP85B402D-000 Amphenol Cables on Demand Amphenol SF-QXP85B402D-000 QSFP28 100GBASE-SR Short-Range 850nm Multi-Mode Optical Transceiver Module (MTP/MPO Connector) by Amphenol XGIGA [QXP85B402D] Datasheet
    MM54HC646J/883 Rochester Electronics LLC Registered Bus Transceiver, Visit Rochester Electronics LLC Buy
    54F646/Q3A Rochester Electronics LLC 54F646 - BUS TRANSCEIVER/REGISTER Visit Rochester Electronics LLC Buy

    16 BIT REGISTER VHDL Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    16 BIT ALU design with verilog hdl code

    Abstract: 8 BIT ALU design with verilog code 16 BIT ALU design with verilog code verilog code for 32-bit alu with test bench verilog code for 32 BIT ALU implementation 32 BIT ALU design with verilog vhdl code 32 bit processor 68000 4 BIT ALU design with verilog vhdl code 16 bit data bus using vhdl 2 bit alu using verilog hdl
    Text: D68000 16/32-bit Microprocessor ver 1.15 ○ OVERVIEW ○ Register indirect D68000 soft core is binary-compatible with the industry standard 68000 32-bit microcontroller. D68000 has a 16-bit data bus and 24-bit address data bus. It is code compatible with the


    Original     		PDF D68000 16/32-bit D68000 32-bit 16-bit 24-bit MC68008 MC68010 MC68020 16 BIT ALU design with verilog hdl code 8 BIT ALU design with verilog code 16 BIT ALU design with verilog code verilog code for 32-bit alu with test bench verilog code for 32 BIT ALU implementation 32 BIT ALU design with verilog vhdl code 32 bit processor 68000 4 BIT ALU design with verilog vhdl code 16 bit data bus using vhdl 2 bit alu using verilog hdl

    vhdl code for shift register using d flipflop

    Abstract: verilog code for 8 bit shift register verilog code for 64 32 bit register verilog code for shift register vhdl code for 8 bit shift register VHDL of 4-BIT LEFT SHIFT REGISTER SRL16 verilog code for 4 bit shift register 8 bit register in verilog verilog code for 8 bit register
    Text: R Using Look-Up Tables as Shift Registers SRLUTs Introduction Virtex-II can configure any look-up table (LUT) as a 16-bit shift register without using the flip-flops available in each slice. Shift-in operations are synchronous with the clock, and output length is dynamically selectable. A separate dedicated output allows the cascading


    Original     		PDF 16-bit 128-bit SRLC16E) SRLC16E h0000; vhdl code for shift register using d flipflop verilog code for 8 bit shift register verilog code for 64 32 bit register verilog code for shift register vhdl code for 8 bit shift register VHDL of 4-BIT LEFT SHIFT REGISTER SRL16 verilog code for 4 bit shift register 8 bit register in verilog verilog code for 8 bit register

    vhdl code 16 bit LFSR

    Abstract: verilog code 16 bit LFSR vhdl code for 32 bit pn sequence generator VHDL 32-bit pn sequence generator vhdl code for shift register using d flipflop vhdl code for pn sequence generator SRL16 fpga cdma by vhdl examples vhdl code for rs232 receiver using fpga vhdl code 16 bit LFSR with VHDL simulation output
    Text: Application Note: Spartan-3 FPGA Series R Using Look-Up Tables as Shift Registers SRL16 in Spartan-3 Generation FPGAs XAPP465 (v1.1) May 20, 2005 Summary The SRL16 is an alternative mode for the look-up tables where they are used as 16-bit shift registers. Using this Shift Register LUT (SRL) mode can improve performance and rapidly lead


    Original     		PDF SRL16) XAPP465 SRL16 16-bit vhdl code 16 bit LFSR verilog code 16 bit LFSR vhdl code for 32 bit pn sequence generator VHDL 32-bit pn sequence generator vhdl code for shift register using d flipflop vhdl code for pn sequence generator fpga cdma by vhdl examples vhdl code for rs232 receiver using fpga vhdl code 16 bit LFSR with VHDL simulation output

    chain linkage

    Abstract: HP3070 M9616 PM5348 CB614351A PM5348-RC PM5348-RC-P
    Text: - PMC_Sierra_Cells for PMC - Sierra revision : VHDL Package and Package Body 1.0 created by : James Lamond Hewlett Packard Canada Ltd date : 20 December 1995 package PMC_Sierra_Cells is use STD_1149_1_1990.all; constant cele0 : CELL_INFO; end PMC_Sierra_Cells;


    Original     		PDF PM5348 descr94, chain linkage HP3070 M9616 CB614351A PM5348-RC PM5348-RC-P

    RTAX2000

    Abstract: ProASIC3 A3P250 RTAX1000S A3P125 A54SX16A A54SX32A APA075 AX125 PAR64 RTAX250S
    Text: CorePCI v5.41 Product Summary Synthesis and Simulation Support Intended Use • Most Flexible High-Performance PCI Offering – Synthesis: ExemplarTM, Synopsys DC / FPGA CompilerTM, and Synplicity® • Simulation: Vital-Compliant VHDL Simulators and OVI- Compliant Verilog Simulators


    Original     		PDF 32-Bit 64-Bit RTAX2000 ProASIC3 A3P250 RTAX1000S A3P125 A54SX16A A54SX32A APA075 AX125 PAR64 RTAX250S

    M9703

    Abstract: HP3070
    Text: BSDL SOURCE CODE - PMC_Sierra_Cells for PMC - Sierra revision : VHDL Package and Package Body 1.0 created by : James Lamond Hewlett Packard Canada Ltd date : 20 December 1995 package PMC_Sierra_Cells is use STD_1149_1_1990.all; constant cele0 : CELL_INFO;


    Original     		PDF pm7375 LASAR-155 pm7375; M9703 HP3070

    0xC704DD7B

    Abstract: vhdl code for ARQ ProASIC3 crc 16 verilog cyclic redundancy check verilog source crc verilog code 16 bit IN SDLC PROTOCOL 80C152 APA150-STD CRC-16
    Text: CoreSDLC Product Summary • Netlist Version – Structural Verilog and VHDL Netlists with and without I/O pads Compatible with Actel's Designer Software Place-and-Route Tool – Compiled RTL Simulation Supported in Actel Libero IDE Intended Use • ISDN D-Channel


    Original     		PDF 80C152 0xC704DD7B vhdl code for ARQ ProASIC3 crc 16 verilog cyclic redundancy check verilog source crc verilog code 16 bit IN SDLC PROTOCOL APA150-STD CRC-16

    usb to parallel IEEE1284 centronics diagram

    Abstract: acia 6850 BEATLES LET IT BE beatles pdf files ACARD cam4 rosa C166 CMD13 CMD16
    Text: Siemens AG Semiconductors MultiMediaCard Adapter Specification and VHDL Reference Preliminary Version 5.1 06.98 Published by Siemens AG, Bereich Halbleiter, HL CC Applications Group St.-Martin-Straße 76, D-81541 München Siemens AG 1998. All Rights Reserved.


    Original     		PDF D-81541 usb to parallel IEEE1284 centronics diagram acia 6850 BEATLES LET IT BE beatles pdf files ACARD cam4 rosa C166 CMD13 CMD16

    vhdl code for watchdog timer

    Abstract: PIC165X 8 BIT ALU design with vhdl code 8 BIT ALU for risc design with verilog code 8 BIT ALU design with verilog/vhdl code DFPIC165X virtex 2 pro vhdl instruction set PIC16C55 PIC16C56
    Text: PIC165X Fast RISC Microcontroller DFPIC165X July 16, 2008 Product Specification AllianceCORE Facts Provided with Core Documentation Digital Core Design User Guide, Design Guide Design File Formats EDIF netlist, Verilog, VHDL Wroclawska 94 41-902 Bytom


    Original     		PDF PIC165X DFPIC165X) DFPIC165X vhdl code for watchdog timer 8 BIT ALU design with vhdl code 8 BIT ALU for risc design with verilog code 8 BIT ALU design with verilog/vhdl code virtex 2 pro vhdl instruction set PIC16C55 PIC16C56

    HP3070

    Abstract: PM5342 PM5342-B1 RSLD
    Text: - PMC_Sierra_Cells for PMC - Sierra revision : VHDL Package and Package Body 1.0 created by : James Lamond Hewlett Packard Canada Ltd date : 20 December 1995 package PMC_Sierra_Cells is use STD_1149_1_1990.all; constant cele0 : CELL_INFO; end PMC_Sierra_Cells;


    Original     		PDF PM5342 SPECTRA-155 HP3070 PM5342-B1 RSLD

    8 bit microprocessor using vhdl

    Abstract: vhdl code scrambler VHDL CODE FOR HDLC controller PLX9080 RFC1619 RFC1662
    Text: PPP8 HDLC Core CC318f February 14, 2000 Product Specification AllianceCORE Facts C ooreEl Core Specifics See Table 1 Provided with Core Documentation Product Brief Datasheet Design Document Test Bench Design Document Test Scripts Design file formats VHDL Compiled, EDIF netlist


    Original     		PDF CC318f) RFC1619 RFC1662 8 bit microprocessor using vhdl vhdl code scrambler VHDL CODE FOR HDLC controller PLX9080 RFC1662

    68hc11 multiple byte transfer using spi

    Abstract: VHDL code for slave SPI with FPGA 68HC11 DS210 M68HC11 MC68HC11 baud rate generator vhdl vhdl code for spi
    Text: OPB Serial Peripheral Interface SPI DS210 (v2.2) July 23, 2002 Summary Product Specification This document presents specifications for the VHDL implementation of Motorola’s Serial Peripheral Interface (SPI) in a Xilinx FPGA. The original specifications closely followed


    Original     		PDF DS210 M68HC11-Rev. M68HC11 Periph8260 68hc11 multiple byte transfer using spi VHDL code for slave SPI with FPGA 68HC11 DS210 MC68HC11 baud rate generator vhdl vhdl code for spi

    vhdl code for i2c master

    Abstract: vhdl code for i2c XCR3256XL-10TQ144C XAPP333 microcontroller using vhdl vhdl code 16 bit microprocessor I2C master controller VHDL code vhdl code up down counter vhdl code for i2c register
    Text: Application Note: CoolRunner CPLD CoolRunner XPLA3 I2C Bus Controller Implementation R XAPP333 v1.0 January 5, 1999 Author: Anita Schreiber Summary This document details the VHDL implementation of an I2C controller in a Xilinx CoolRunner™ XPLA3 256 macrocell CPLD. CoolRunner CPLDs are the lowest power CPLDs available,


    Original     		PDF XAPP333 vhdl code for i2c master vhdl code for i2c XCR3256XL-10TQ144C XAPP333 microcontroller using vhdl vhdl code 16 bit microprocessor I2C master controller VHDL code vhdl code up down counter vhdl code for i2c register

    CY7C371

    Abstract: CY7C373 CY7C375 FLASH370 MAX7000 374I 4-bit loadable counter
    Text: The FLASH370i Family Of CPLDs and Designing with Warp2 This application note covers the following topics: 1 a general discussion of complex programmable logic devices (CPLDs), (2) an overview of the FLASH370i™ family of CPLDs, and (3) using the Warp2 VHDL Compiler for the FLASH370i family.


    Original     		PDF FLASH370iTM FLASH370i CY7C371 CY7C373 CY7C375 FLASH370 MAX7000 374I 4-bit loadable counter

    vhdl code for i2c

    Abstract: XCR3256XL-10TQ144C I2C master controller VHDL code interrupt controller vhdl code download microcontroller using vhdl high level block diagram for i2c controller I2C CODE OF READ IN VHDL Philips MBB vhdl code for i2c register XAPP333
    Text: Application Note: CoolRunner CPLDs R XAPP333 v1.5 November 7, 2000 CoolRunner XPLA3 I2C Bus Controller Implementation Summary This document details the VHDL implementation of an I2C controller in a Xilinx CoolRunner® XPLA3 256 macrocell CPLD. CoolRunner CPLDs are the lowest power CPLDs available,


    Original     		PDF XAPP333 vhdl code for i2c XCR3256XL-10TQ144C I2C master controller VHDL code interrupt controller vhdl code download microcontroller using vhdl high level block diagram for i2c controller I2C CODE OF READ IN VHDL Philips MBB vhdl code for i2c register XAPP333

    I2C master controller VHDL code

    Abstract: vhdl code for i2c XCR3256XL-10TQ144C Philips MBB XAPP333 XCR3256
    Text: Application Note: CoolRunner CPLDs R XAPP333 v1.4 July 21, 2000 CoolRunner XPLA3 I2C Bus Controller Implementation Summary This document details the VHDL implementation of an I2C controller in a Xilinx CoolRunner® XPLA3 256 macrocell CPLD. CoolRunner CPLDs are the lowest power CPLDs available,


    Original     		PDF XAPP333 I2C master controller VHDL code vhdl code for i2c XCR3256XL-10TQ144C Philips MBB XAPP333 XCR3256

    vhdl code for i2c Slave

    Abstract: I2C master controller VHDL code high level block diagram for i2c controller vhdl code for i2c vhdl code for i2c master microcontroller using vhdl XAPP315 i2c vhdl code vhdl code for 4 bit shift register
    Text: Application Note: CoolRunner CPLD Implementing an I2C Bus Controller in a CoolRunner™ CPLD R XAPP315 v1.0 October 25, 1999 Application Note Summary This document details the VHDL implementation of an I2C controller in a Xilinx CoolRunner™ 128 macrocell CPLD. CoolRunner CPLDs are the lowest power CPLDs available and thus are


    Original     		PDF XAPP315 vhdl code for i2c Slave I2C master controller VHDL code high level block diagram for i2c controller vhdl code for i2c vhdl code for i2c master microcontroller using vhdl XAPP315 i2c vhdl code vhdl code for 4 bit shift register

    vhdl code for i2c Slave

    Abstract: XAPP315 vhdl code for i2c I2C master controller VHDL code vhdl code for i2c master I2C master controller code i2c/i2c/ST7032
    Text: Application Note: CoolRunner CPLDs R XAPP315 v1.2 May 2, 2000 Implementing an I2C Bus Controller in a CoolRunner CPLD Summary This document details the VHDL implementation of an I2C controller in a Xilinx CoolRunner® 128 macrocell CPLD. CoolRunner CPLDs are the lowest power CPLDs available and thus are


    Original     		PDF XAPP315 XAPP315 vhdl code for i2c Slave vhdl code for i2c I2C master controller VHDL code vhdl code for i2c master I2C master controller code i2c/i2c/ST7032

    XAPP348

    Abstract: spi master vhdl code for spi 8 bit shift register 68HC11 XAPP349 XAPP386 XC2C256 XCR3256XL CPLD CoolRunner CPLD
    Text: Application Note: CoolRunner CPLD CoolRunner Serial Peripheral Interface Master R XAPP348 v1.2 December 13, 2002 Summary This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx CoolRunner XPLA3 CPLD. CoolRunner CPLDs are the lowest power CPLDs


    Original     		PDF XAPP348 XCR3256XL XC2C256 XAPP386, XAPP348 spi master vhdl code for spi 8 bit shift register 68HC11 XAPP349 XAPP386 CPLD CoolRunner CPLD

    XAPP348

    Abstract: 68HC11 XAPP349 XAPP350 XC2C256 XCR3256XL Bidirectional Bus VHDL vhdl code for spi vhdl spi interface
    Text: Application Note: CoolRunner CPLD R CoolRunner Serial Peripheral Interface Master XAPP348 v1.1 October 1, 2002 Summary This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx CoolRunner XPLA3 CPLD. CoolRunner CPLDs are the lowest power CPLDs


    Original     		PDF XAPP348 XCR3256XL XC2C256 XAPP348 68HC11 XAPP349 XAPP350 Bidirectional Bus VHDL vhdl code for spi vhdl spi interface

    xilinx uart verilog code

    Abstract: vhdl code for rs232 receiver vhdl code for uart communication vhdl code for shift register vhdl code for serial transmitter 16 bit register vhdl vhdl code for rs232 interface UART using VHDL uart verilog code vhdl code for 8 bit shift register
    Text: Application Note: CPLD R UARTs in Xilinx CPLDs XAPP341 v1.1 April 17, 2000 Summary This application note provides a functional description of VHDL and Verilog source code for a UART. The code is used to target the XC95144 and XCR3128 CPLDs. The functionality of the


    Original     		PDF XAPP341 XC95144 XCR3128 RS232. XAPP341 xilinx uart verilog code vhdl code for rs232 receiver vhdl code for uart communication vhdl code for shift register vhdl code for serial transmitter 16 bit register vhdl vhdl code for rs232 interface UART using VHDL uart verilog code vhdl code for 8 bit shift register

    vhdl code for rs232 receiver

    Abstract: verilog code for uart communication vhdl code for uart communication xilinx uart verilog code uart verilog code verilog code for serial transmitter vhdl code for serial transmitter interface of rs232 to UART in VHDL UART using VHDL 16 bit register vhdl
    Text: Application Note: CPLD R UARTs in Xilinx CPLDs XAPP341 v1.2 November 28, 2000 Summary This application note provides a functional description of VHDL and Verilog source code for a UART. The code is used to target the XC95144 and XCR3128XL CPLDs. The functionality of


    Original     		PDF XAPP341 XC95144 XCR3128XL RS232. XAPP341 XCR3128 vhdl code for rs232 receiver verilog code for uart communication vhdl code for uart communication xilinx uart verilog code uart verilog code verilog code for serial transmitter vhdl code for serial transmitter interface of rs232 to UART in VHDL UART using VHDL 16 bit register vhdl

    T9541

    Abstract: HP3070 PM5347
    Text: - PMC_Sierra_Cells for PMC - Sierra revision : VHDL Package and Package Body 1.0 created by : James Lamond Hewlett Packard Canada Ltd date : 20 December 1995 package PMC_Sierra_Cells is use STD_1149_1_1990.all; constant cele0 : CELL_INFO; end PMC_Sierra_Cells;


    Original     		PDF PM5347 T9541 HP3070

    XAPP386

    Abstract: simple microcontroller using vhdl microcontroller using vhdl spi master 68HC11 XAPP348 XC2C256 XCR3256XL vhdl code for spi
    Text: Application Note: CoolRunner-II CPLD CoolRunner-II Serial Peripheral Interface Master R XAPP386 v1.0 December 24, 2002 Summary This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx CoolRunner -II CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available,


    Original     		PDF XAPP386 XC2C256 XCR3256XL XAPP348, XAPP386 simple microcontroller using vhdl microcontroller using vhdl spi master 68HC11 XAPP348 vhdl code for spi